Generic Command FIFO—20-bit Width and 32-bit Depth

31:20

19

18

17

16

15:14

13

12

11:10

9

8

7:0

Reserved

31:20

Reserved.

Poll

19

This bit is applicable when receive is enabled.

1'b0: Once.

1'b1: Poll.

When set to 1'b1, the generic Quad-SPI controller keeps reading the data until it matches the received data with the POLL_DATA field data from the poll register, depending on the configured masking in poll register.

Stripe

18

1'b0: Do not Stripe. Mirror the same data on the lower and upper data buses.

1'b1: Stripe data across the lower and upper data buses.

Only byte stripe is supported.

The lower data bus uses even bytes, i.e., byte 0, 2, 4 …, of a data word. The upper data bus uses odd bytes, i.e., byte 1, 3, 5, …, of a data word.

Stripe is applicable when the data bus select is 2'b11, and both upper and lower data buses are active.

Stripe = 1'b0 is not applicable when receive = 1'b1.

Receive

17

1'b0: Discard RX data.

1'b1: Capture/receive data.

When [receive, transmit, data_xfer] = [0,0,1], it represents a dummy cycle.

Transmit

16

1'b0: Write dummies/Zero pump

1'b1: Transmit

When [receive, transmit, data_xfer] = [0,0,1], it represents a dummy cycle.

Data bus select

15:14

2'b00: No bus.

2'b01: Lower bus select.

2'b10: Upper bus select.

2'b11: Both lower and upper buses.

The number of data bus bits depends on the SPI mode.

SPI mode: the data bus is 1 bit wide.

Dual-SPI mode: the data bus is 2 bits wide.

Quad-SPI mode: the data bus is 4 bits wide.

The lower clock (QSPI0_SCLK sclk_out) is driven when the lower bus is selected. The upper clock (QSPI1_SCLK) is driven when the upper bus is selected.

cs_upper

13⁽¹⁾

1'b0: Do not drive the upper chip select.

1'b1: Drive the upper chip select.

cs_lower

12⁽¹⁾

1'b0: Do not drive the lower chip select.

1'b1: Drive the lower chip select.

SPI mode

11:10

2'b00: Reserved.

2'b01: SPI.

2'b10: Dual-SPI.

2'b11: Quad-SPI.

Exponent

9

0: Absolute.

1: Exponent.

When data_xfer = 1, this field is used.

When data_xfer = 1, and because the immediate_data is 8 bits, the maximum data to be transmitted/received is 2⁸ = 256 bits. To transmit/receive more than 256 bits of data, use the exponent bit.

For example, when reading 1G bytes from the SPI flash, the generic FIFO fields uses the following contents.

data_xfer = 1'b1
exponent = 1'b1
immediate_data = 8'h1E (decimal 30).

The number of data bytes = 2³⁰ = 1G bytes.

Notes:

1.When both bits {13:12} are set to 1, it indicates the configuration for the dual parallel mode. Both of these bits are set by the driver.

data_xfer

8

1'b0: The immediate_data is used as immediate.

1'b1: The immediate_data is used as the number of data bytes to be sent/received.

immediate_data

7:0

When data_xfer = 1'b0, and transmit is a non zero, these bits are sent on the SPI interface.

When data_xfer = 1'b1, and transmit is non zero, this field specifies the number of data bytes sent from the TXFIFO.

When data_xfer = 1'b1, and receive is non zero, this field specifies the number of data bytes to read into the RXFIFO.

The maximum number of data bytes allowed are 2²⁸ in DMA and PIO mode.

When data_xfer = 1'b1, RX = 1'b0 and TX = 1'b0, this field specifies the number of dummy SCLK cycles sent on the SPI interface.

When data_xfer = 1'b0, RX = 1'b0, data bus select is non zero, TX = 1'b0, and cs_lower/cs_upper is non zero, this field specifies the CS setup time using the number of reference clock cycles.

When data_xfer = 1'b0, RX = 1'b0, data bus select is non zero, TX = 1'b0, and cs_lower/cs_upper is zero, this field specifies the CS hold time using the number of reference clock cycles.