Task |
SD{0, 1} |
Register Field |
Register Offset |
Bits |
Value |
---|---|---|---|---|---|
Reset the controller. |
reg_softwarereset |
swreset_for_all |
0x2f |
0 |
1b'1 |
Wait until device has been reset. |
reg_softwarereset |
swreset_for_all |
0x2f |
0 |
Read operation |
Read and save controller capabilities(1). |
reg_capabilities |
ALL |
0x40 |
63:0 |
Read operation |
Select voltage 3.3V and enable bus power. |
reg_powercontrol |
pwrctrl_sdbusvoltage | pwrctrl_sdbuspower |
0x29 |
3:1,0 |
4b'1111 |
Change the clock frequency to 400 KHz (see Table: SD Clock Frequency Change). |
|||||
Select 32-bit ADMA2 mode. |
reg_hostcontrol1 |
hostctrl1_dmaselect |
0x28 |
4:3 |
2b'10 |
Enable all interrupt status except card interrupt initially. |
reg_normalintrstsena |
ALL |
0x34 |
15:0 |
0xFEFF |
Enable error interrupts. |
reg_errorintrstsena |
ALL |
0x36 |
12:0 |
Write 3FF h |
Disable all interrupt signals. |
reg_normalintrsigena |
ALL |
0x38 |
15:0 |
Write 0000h |
Disable all error signals. |
reg_errorintrsigena |
ALL |
0x40 |
12:0 |
Write 000h |
Transfer mode register: default value. DMA enabled, block count enabled, data direction card to host (read). |
reg_transfermode |
xfermode_dmaenable | xfermode_blkcntena | xfermode_dataxferdir |
0x0C |
4, 1, and 0 |
Write 1 to all bits |
Set block size to 512 by default. |
reg_blocksize |
xfer_blocksize |
0x04 |
11:0 |
Write 200h |
Notes: 1.the re-tuning interval in the SDIO capabilities register is determined by the IOU_SLCR.SD_CONFIG_REG3 [SD0_RETUNETMR] and [SD1_RETUNETMR] fields. The default value for this register is set to 0x8, which enables auto refresh at 128s. The software driver must ensure programming this register to the appropriate value based on your specific application requirements. |