The PLL control registers are in the CRL_APB (LPD) and CRF_APB (FPD) register sets.
Table 37-4: System PLL Clock Control Register Settings
|
Register Name
|
Reset value,
Address offset (LPD, FPD)
|
Register Parameter
|
Reset State
|
Pre-FSBL
|
Comments
|
|
RPLL_CTRL
|
0001_2C09 h,
LPD 0x030
|
[RESET]
[BYPASS]
[FBDIV]
[DIV2]
[PRE_SRC]
[POST_SRC]
|
Held in reset.
Bypass enabled.
2C h.
Divide by 2.
PS_REF_CLK.
PS_REF_CLK.
|
|
|
|
IOPLL_CTRL
|
0001_3200 h,
LPD 0x020
|
[RESET]
[BYPASS]
[FBDIV]
[DIV2]
[PRE_SRC]
[POST_SRC]
|
Held in reset.
Bypass enabled.
2C h.
Divide by 2.
PS_REF_CLK.
PS_REF_CLK.
|
Released from reset.
|
|
|
APLL_CTRL
|
0001_2C09 h,
FPD 0x020
|
[RESET]
[BYPASS]
[FBDIV]
[DIV2]
[PRE_SRC]
[POST_SRC]
|
Held in reset.
Bypass enabled.
2C h.
Divide by 2.
PS_REF_CLK.
PS_REF_CLK.
|
|
|
|
DPLL_CTRL
|
0000_2C09 h,
FPD 0x02C.
|
[RESET]
[BYPASS]
[FBDIV]
[DIV2]
[PRE_SRC]
[POST_SRC]
|
Held in reset.
Bypass enabled.
2C h.
Pass-through.
PS_REF_CLK.
PS_REF_CLK.
|
Released from reset.
|
|
|
VPLL_CTRL
|
0000_2809 h,
FPD 0x038.
|
[RESET]
[BYPASS]
[FBDIV]
[DIV2]
[PRE_SRC]
[POST_SRC]
|
Held in reset.
Bypass enabled.
28 h.
Divide by 2.
PS_REF_CLK.
PS_REF_CLK.
|
|
|
|
IOPLL_TO_FPD_CTRL
|
0000_0400 h,
LPD 0x044.
|
[DIVISOR0]
|
04 h
|
|
|
|
RPLL_TO_FPD_CTRL
|
0000_0400 h,
LPD 0x048.
|
[DIVISOR0]
|
04 h
|
|
|
|
APLL_TO_LPD_CTRL
|
0000_0400 h,
FPD 0x048.
|
[DIVISOR0]
|
04 h
|
|
|
|
DPLL_TO_LPD_CTRL
|
0000_0400 h,
FPD 0x04C.
|
[DIVISOR0]
|
04 h
|
|
|
|
VPLL_TO_LPD_CTRL
|
0000_0400 h,
FPD 0x050.
|
[DIVISOR0]
|
04 h
|
|
|