DMA Interrupt Accounting

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The DMA channel does not update descriptors in memory. The feedback when the descriptor is done is provided by a SRC/DST done interrupt along with an interrupt accountings counter (control register). The following interrupt accounting scheme is implemented on each DMA channel, on both the SRC and DST sides.

The software can selectively request a completion interrupt on descriptors. Once a descriptor is processed, the DMA increments the interrupt accountings counter. The definition of a descriptor done is different on the SRC and DST sides.

A SRC descriptor done interrupt is generated once the DMA is done reading all the data corresponding to the source buffer descriptor. The SRC descriptor done interrupt does not guarantee that data is written at a destination location. Data can still be in a shared common buffer.

A DST descriptor done interrupt is generated once the DMA channel receives a response to the last AXI write of the buffer corresponding to the DMA buffer descriptor. The DST done interrupt ensures that data has been written to the memory location.

An interrupt is generated to the software as soon as the interrupt accounting’s count transitions to non-zero. When the software takes this interrupt, it should also read the interrupt accountings register. Count provides the number of processed descriptors with interrupt enabled. This counter is cleared on read (due to coherency). Implementing this scheme eliminates the need for a timeout mechanism. It also provides flexibility to the software to enable an interrupt on a required descriptor.

The DMA channel implements a separate 32-bit interrupt account counter for the source and destination sides. If the software does not read/clear the counter for a long time, this counter can overflow. The DMA generates an interrupt to indicate the overflow condition on the interrupt accounting counter. If a counter over flows on the last descriptor of a DMA transfer (DMA DONE), then the interrupt accounting counter overflow interrupt is generated two clock cycles after the DMA done interrupt due to asynchronous boundary crossing logic.