Zynq UltraScale+ Device Technical Reference Manual
Introduction
Introduction to the UltraScale Architecture
Application Overview
System Block Diagram
Power Domains and Islands
High-Speed Serial I/O
GTR Transceivers
GTY Transceivers
MIO and EMIO
Platform Management and Boot
Functional Units and Peripherals
Device ID Codes
JTAG IDCODE
IP Revisions
System Software
System Features Assigned by Software
Documentation
Signals, Interfaces, and Pins
Introduction
Dedicated Device Pins
Power Pins
Clock, Reset, and Configuration Pins
JTAG Interfaces
MIO Pins
DDR Memory Controller I/O
PS GTR Serial Channel Device Pins
PS-PL Signals and Interfaces
PS-PL Voltage Level Shifters
Processor Communications
System Error Signals
MIO-EMIO Signals and Interfaces
Miscellaneous Signals and Interfaces
Dedicated Stream Interfaces
DisplayPort Media Interfaces
Clock Signals
Timer Signals
System Debug Signals and Interfaces
PS-PL AXI Interfaces
Application Processing Unit
Introduction
Cortex-A53 MPCore Processor Features
Arm v8 Architecture
Security State
APU Functional Units
Instruction Fetch Unit
Data Processing Unit
Advanced SIMD and Floating-point Extension
Cryptography Extension
Translation Lookaside Buffer
Data-side Memory System
Store Buffer
Bus Interface Unit and SCU Interface
Snoop Control Unit
L2 Memory Subsystem
Cache Protection
Debug and Trace
Generic Interrupt Controller
Timers
APU Memory Management Unit
System Virtualization
APU Virtualization
Interrupt Virtualization
Timer Virtualization
System Coherency
I/O Coherency
Full Two-way Coherency
ACE Interface
ACP Interface
APU Power Management
Power Islands
Power Modes
Normal State
Standby State
MPCore Wait for Interrupt
MPCore Wait for Event
L2 Wait for Interrupt
Individual MPCore Shutdown Mode
Cluster Shutdown Mode with System Driven L2 Flush
Clocks and Resets
Performance Monitors
System Registers
System Memory Virtualization Using SMMU Address Translation
Translation Buffer Unit
Translation Control Unit
TBU Entry Updates
SMMU Architecture
Stage 1 SMMU Translation
Stage 2 SMMU Translation
TLB Maintenance Operations
SMMU Clocks and Resets
Real-time Processing Unit
Introduction
Real-time Processing Unit Features
Cortex-R5F Processor Functional Description
RPU Pin Configuration
RPU CPU Configuration
Split/Lock
Lock-Step Operation
Error Correction and Detection
Interrupt Injection Mechanism
Level2 AXI Interfaces
Memory Protection Unit
Events and Performance Monitor
Power Management
Exception Vector Pointers
System Register Overview
Tightly Coupled Memory
Tightly Coupled Memory Functional Description
Normal (Split) Operation
Lock-step Operation
Tightly Coupled Memory Address Map
TCM Access from a Global Address Space
Lock-step Sequence in Cortex-R5F Processors
Graphics Processing Unit
Introduction
Features
Power Domains
Clocking Domain
Performance
Graphics Processing Unit Functional Description
Geometry Processor
Vertex Processing
Vertex Shader
Vertex Loader
Vertex Shader Core
Vertex Storer
Polygon List Builder
Pixel Processor
Pixel Processor Fragment Shader
Graphics Processing Unit Level 2 Cache Controller
Graphics Processing Unit Memory Management Unit
Graphics Processing Unit Programming Model
Power Management in GPU
Programming the GPU
Graphics Processing Unit Register Overview
Platform Management Unit
Introduction
Power Modes
Battery Powered Mode
Low-Power Operation Mode
Full-Power Operation Mode
PMU System-level View
Functional Description
PMU Processor
PMU Processor Interfaces
PMU Clocking
PMU Reset
PMU RAM
PMU ROM
MBIST Functionality
Scan Clear Functionality
PMU Interconnect
PMU I/O Registers
PMU Global Registers
PMU GPIs and GPOs
PMU Programmable Interval Timers
PMU Interrupts
MIO Pin Considerations
PMU Error Handling and Propagation Logic
Operation
Interacting with the PMU
Power Down
Power Up
Use Case for Power Down and Power Up by PMU
APU Power Down
Direct Power Down
Requested Power Down
APU Core Power Up
PMU Operation After a Wake-up
Wake-up Through MIO
Wake-up on USB
Wake-up on Ethernet
Wake on Real-time Clock
Wake through DAP
Direct Wake by the APU or Cortex-R5F
Wake through GIC Proxy
Deep-sleep Mode
Deep-sleep Mode Programming Model/Example
System Configuration prior to Sleep
System Configuration during Sleep
Power Down Procedure
Wake Procedure
Isolation Request
Reset Services
Programming Model
Register Overview
MIO Signals
Real Time Clock
Introduction
Functional Description
RTC Operation
Block Diagram
Interfaces and Signals
Seconds Counter
Calibration
RTC Accuracy
Calibration Algorithm
Dynamic Oscillator Inaccuracy
External Clock Crystal and Circuitry
Battery Selection
RTC Register List
Programming Model
Programming Notes
Programming Sequences
init rtc
Set Time
Programming Example – Periodic Alarm
Functional Safety
Introduction
Safety Features overview
Single Point Fault Detection Measures
Common Cause Failure Measures
Latent Fault Measures
Isolation Measures
Additional Measures
System Monitors
Introduction
Features
Unit Architectures
Sensor Channels
Alarms
Block Diagrams
PL SYSMON
PS SYSMON
Comparison of PS SYSMON and PL SYSMON
On-chip Thermal Diode
Safety Considerations
Set Operating Limits
Monitor Supply Voltages
Monitor Temperature
Safety User Manual
Functional Description
Sensor Channels
Two Classes of Sensor Channels
Sensor Channel Tables
PS SYSMON Sensor Channels
PL SYSMON Sensor Channels
Measurement Registers
Average Measurements
Measurement Registers in AMS
PS SYSMON Analog_Bus
Temperature Sensors
Minimum and Maximum Result Registers
Sequencer Channel Control
Low-Rate Sampling
Long Acquisition Time
Input Sampling Circuits
Unipolar Mode
Bipolar Mode
Sensor Alarm Types
Voltage Alarms
Normal Temperature Alarms
Upper Alarm Threshold
Lower Alarm Threshold
Over Temperature Alarms
Alarm Interrupt Control
Alarm Signal Routing
Interrupts
End of Sequence Event
End of Conversion (EOC) Event
Register Address Decode Error (APB)
Interrupt Control Registers
Status/Clear
Enable, Disable Mask
Debug Environment
Operating Modes
Single-channel Mode
Default Sequence Mode
Sequencer Modes
Programming Examples
Example – Continuous Loop Mode
Example – Single Pass Sequence Mode
Thermal Management
Normal Temperature Alarm
Critical Over-Temperature Shutdown
OT Alarm
Register Sets
Register Access via APB Slave Interface
AMS Register Set Access
PSSYSMON Register Set Access
PLSYSMON Register Set Access
PL SYSMON Register Access Arbitration
Register Access via PL Fabric andSerial Channels
DRP Slave Interface in PL Fabric
PL TAP Controller Interface via JTAG
I2C Serial Interface via Device Pins
PM Bus
System Interfaces
Clocks
Reset Sources
PL SYSMON
PS SYSMON
Reset States
Measurement Registers
Configuration Registers
Power
PS SYSMON Unit
PL SYSMON Unit
Control and Monitor Signals
Alarms Signals
IRQ Interrupt
Sequence Triggers
End-of-Conversion and End-of-Sequence Events
System Addresses
Introduction
Global Address Map
32-bit (4 GB) Address Map
36-bit (64 GB) Address Map
40-bit (1 TB) Address Map
System Address Map Interconnects
System Address Map
PL AXI Interface
System Address Register Overview
System-level Control Registers
Private CPU Registers
PS I/O Peripherals Registers
PS System Registers
Boot and Configuration
Introduction
Boot Flow
Boot Modes
Golden Image Search
Fallback
Boot Image Format
I/O Configuration Detection
4-bit I/O Detection
8-bit I/O Detection
Functional Units
Secure Stream Switch
CSU DMA
Loopback Mode
PL Configuration
PCAP Isolation Wall Control
CSU BootROM Error Codes
PL Bitstream
Register Overview
Configuration Programming Model
Load the PL Bitstream
Initialize PCAP Interface
Write a Bitstream Through the PCAP
Wait for the PL Done Status
Programming the CSU DMA
Trigger a CSU DMA Transfer
Wait for CSU DMA Done
Security
Introduction
Device and Data Security
Configuration Security Unit (CSU) Introduction
Secure Processor Block
Crypto Interface Block
CSU Resets
Register Access
Tamper Monitoring and Response
Lockdown
Non-Secure Lockdown
Secure Lockdown
Emulating a Tamper Event
Staged Response to a Tamper Event
Key Management
Battery-Backed RAM
BBRAM Programming
BBRAM Readback Protections
BBRAM Zeroization
BBRAM Key Agility
eFUSE
eFUSE Programming
eFUSE Readback Protections
eFUSE Zeroization
Key Update Register
Operational Key
Storing Keys in Obfuscated Form
Storing Keys in Encrypted Form (Black)
PUF Helper Data
PUF Operations
PUF Control eFUSEs
PUF Characterization, Testing, and Ordering
Key Management Summary
Protecting Test Interfaces
JTAG Interface Protections
PL Clearing
Device DNA Identifiers
Error Output Disable
Cryptographic Acceleration
AES-GCM
Initialization Vector Register
Programming AES-GCM Engine
SHA-3/384
Programming SHA-3 Engine
RSA Accelerator
Programming the RSA Engine
Secure Non-Volatile Storage
Security Related eFUSEs
PS eFUSEs
PL eFUSEs
Secure Boot
Secure Boot Introduction
Secure Boot Summary
Hardware Root Of Trust Secure Boot Details
Device Provisioning
Boot Operation
System Configuration
Systems with external DRAM
Systems without external DRAM
DPA Resistance
Rolling Keys
Integration and Test Support (BH RSA Option)
Hardware Root of Trust Only Boot (Auth_Only Option)
Key Revocation
PPK Revocation
Standard SPK Revocation
Enhanced SPK Revocation
Revocation as a Tamper Penalty
Encrypt Only Secure Boot Details
Loading Bitstreams
Secure Boot Image Format
Boot Options
Minimizing Use of the AES Boot Key (OP Key Option)
Protect Device Key in Development Environment with OP Key
Interrupts
Introduction
GIC Features
RPU-specific GIC Features
APU-specific GIC Features
GIC Proxy Interrupts
System Interrupts
GIC Interrupt System Architecture
Interrupt Block Diagram
RPU GIC Interrupt Controller
Software Generated Interrupts
Shared Peripheral Interrupts
SPI Interrupt Sensitivity
Interrupt Prioritization
APU GIC Interrupt Controller
Peripheral Interrupts
Software-generated Interrupts
Virtualization Extensions
Virtual Interrupt
APU Interrupt Partitioning
APU Interrupt Grouping and Virtualization
IPI Interrupts and Message Buffers
Interrupt Architecture
Interrupt Register Descriptions
Interrupt Register Channels
Message Passing Architecture
Register and Buffer Summary
Programming
Generate an Interrupt
Determine the Source of Interrupt
Send an IPI Communication
Receive an IPI Communication
Interrupt Registers
GIC Proxy Interrupts
Interrupt Status Register
Interrupt Mask Register (IMR_REG)
Interrupt Enable and Interrupt Disable Registers
Interrupts to PMU
CPU Private Peripheral Interrupts
RPU Private Interrupts
APU Private Interrupts
GIC Address Map
Register Overview
Programming Examples
Clearing Pending Interrupts from the APU GICv2
Programming Model IPI
Example: Initiate an IPI
Example: Receive an IPI
Enable the Interrupt
Disable the Interrupt
Timers and Counters
Introduction
System Block Diagram
APU MPCore System Counter
Features
Applications
Event Streams
Programming
Generic Timer Programming
Register Overview
Register Access
APU Core Private Physical and Virtual Timers
System Timer
Features
Physical Timer
Physical Counter
Accessing the Physical Counter
Virtual Timer
Virtual Counter
Accessing the Virtual Counter
Register Access
Accessing the Timer Registers
EL1 Physical Timer
Virtual Timer
EL2 Physical Timer
Register Overview
Triple-timer Counters
TTC Counter Features
TTC Block Diagram
TTC Functional Description
Initialization
Prescaler
Counter Module
Interrupt Module
Modes of Operation
Interval Mode
Overflow Mode
Event Control Timer Operation
Register Overview
TTC Programming Examples
TTC Programming
System Watchdog Timers
SWDT Functional Description
Interrupt to RPU and APU GIC Interrupt Controllers
Watchdog Enabled on Reset
CPU Debug
SWDT I/O Control and Configuration Register Sets
SWDT Register Overview
SWDT Register Overview
SWDT Programming Sequence
Programming Model
Enable Sequence
SWDT Programming Examples
Watchdog Timer Programming
Watchdog Timer Flowcharts
MIO - EMIO Signals
PS Interconnect
Introduction
Features
Block Diagram
FPD Main Switch
Cache Coherent Interconnect
Full Coherency
I/O Coherency
ACP Coherency
Interconnect Submodules
AMD Memory Protection Unit
AMD Peripheral Protection Unit
System Memory Management Unit
AXI Timeout Block
AXI and APB Isolation Block
Quality of Service Block
PS-PL AXI Interfaces
IOP Bus Masters
ATB Timeout Description
Instances
Programming
AXI Performance Monitor
Features
Implementation
PS Instances
Event Metric List
Register Overview
Programming Example - Read Byte Count on DDR Port 3
Programming Example – Metric Counter
Quality of Service
AXI Traffic Types
Low Latency (High Priority) Masters
High Throughput (Best Effort) Masters
Isochronous (Video and Audio Class) Masters
QoS Subsystems
QoS Regulator
Outstanding Command Issuing Control
Command Issue Rate Control
QoS Controller
QoS Virtual Networks in CCI-400
DDR Controller QoS
Interconnect Register Overview
System Protection Units
Introduction
Secured Register Sets
Write-Protected Registers
Processor-only Accessible Registers
TrustZone Security
SMMU Protection
XPPU and XMPU Protection Units
Use Case Examples
Terminology
TrustZone
Architecture
Master and Slave Security Profiles
TrustZone Profile Table
TrustZone System-level Control Registers
Register Write Protection Lock
PL TrustZone Extension
DDR TrustZone Protection
APU MPCore TrustZone Model
SMMU Protection on CCI Slave Ports
Address Translation Isolation (Native, Non-Virtualized Scenario)
Guest Domain Isolation (Virtualized Scenario)
TBU Instances
XMPU Protection of Slaves
Architecture
XMPU Regions
Poison Attribute Signals
Poison Address
Region Checking Operation
Master ID Validation
Security Validation
Instances
Error Handling
XMPU Error Handling
Configuration
Alignment and Poison Configuration
Block Diagram
XMPU Register Set Overview
XPPU Protection of Slaves
Features
Instances
XPPU Operation
Master ID List
Aperture Permission List
Entry Format
Aperture Permission List
Protected Addresses
Permission Checking
Error Handling
Sync and Async Abort
XPPU Self-Protection
Master ID Validation
Master IDs List
PS-PL AXI Interfaces
XPPU Register Set Overview
Lock Unused Memory Attribute
Programming Example
Use Cases
Program the DDR XMPUs
Program the FPD XMPU
Program the OCM XMPU
Program the XPPU
Write-Protected Registers Table
CRF APB Registers
Other Write-Protected Registers
Security and Safety Errors
Security Error
Safety Error
AIB Isolation Functionality
Instances
Programming
DDR Memory Controller
Introduction
System Memories
Features
DDR PHY Features
DDR Memory Types, Densities, and Data Widths
DDR DRAM Pins
Power and Reset
System Block Diagram
AMD Memory Protection Unit
DDR QoS Controller
Prevention of Head-of-Line Blocking
Traffic Classes
Type Register
Control Registers
Threshold Registers
Interrupt Sources
DDR Subsystem Overview
AXI Port Interface
Read Address Channel
Write Address Channel
Read Data and Response Channel
Write Data Channel
Write Response Channel
Exclusive Access
XMPU Poisoned Transaction
Port Arbiter
Read/Write Arbitration
Read and Write Priorities
Port Command Priority
Round-Robin Arbitration
Port Arbiter Masking
DDR Controller Address Map
Address Map
SDRAM Address Mapping
Address Collision Handling
Error Correcting Code
ECC Initialization
ECC Error Behavior
Data Mask During ECC Mode
Encoding for Corrected Bit Number
ECC Programming Model
Monitoring ECC Status
ECC Poisoning
ECCSTAT Register DDRC for Encoding of ECC Corrected Bit Number
Functional Description
DDR PHY PLL Control
PHY Utility Block
PHY Description
Controller Initialization
PHY Initialization
DRAM Initialization
Data Training
Dynamic DDR Configuration
Programming Topics
PHY General Status Register
Impedance Calibration
PLL Initialization
Delay Line Calibration
DRAM Initialization
CA Training (LPDDR3 Only)
Write Leveling
Read Leveling
Write DQS2DQ Training (LPDDR4 only)
Write Latency Adjustment
Data Eye Training
Read Bit Deskew
Write Bit Deskew
Read Eye Centering
Write Eye Centering
VREF Training (DDR4 and LPDDR4 only)
Register Overview
DDR QoS Control Registers
DDR Controller Registers
DDRPHY Registers
Programming Model
Programming Modes
Dynamic Registers
Dynamic - Refresh Related Registers
Quasi Dynamic Registers
Group 1: Registers that can be written when no read/write traffic is present at the DFI
Group 2: Registers that can be written in self-refresh, DPD, and MPSM modes
Group 3: Registers that can be written when controller is empty
Group 4: Registers that can be written depending on MSTR.frequency_mode
Power Saving Features
Automatic Low Power Modes
Precharge Power Down
Deep Power-Down
Entering Deep Power-down
Exiting Deep Power-down
Self Refresh
Maximum Power Saving
Entering Maximum Power Saving Mode
Exiting Maximum Power Saving Mode
Asserting PWRCTL.en_dfi_dram_clk_disable to Disable the Clocks to DRAM
DDR Initialization
PHY Initialization
DRAM Initialization
Data Training
Reading DRAM Configuration Mode Registers
Mode Register Accesses
Multi-Purpose Register (DDR4 Only)
On-chip Memory
Introduction
Features
On-chip Memory Functional Description
Address Mapping
Mapping Summary
64-bit ECC Support
Low Power Operation
On-chip Memory Register Overview
On-chip Memory Programming Model
Inject Fault
Check for Error
Read Correctable Error Register Set
Read Uncorrectable Error Register Set
DMA Controller
Introduction
Features
DMA Controller Functional Description
DMA Architecture
Common Buffer
AXI Read Arbiter
AXI Write Arbiter
DMA Channel
DMA Data Flow
DMA Model
DMA Modes
Simple DMA Mode
Scatter Gather DMA Mode
Descriptor Format
Linear Descriptor Use Case
Linked-list Descriptor Use Case
Hybrid Descriptor Use Case
Buffer Descriptor Summary
Buffer Descriptor Format
DMA Performance Requirements
DMA Interrupt Accounting
DMA Over Fetch
DMA Transaction Control
Outstanding Transactions
Rate Control
Flow Control Interface
FCI Considerations
DMA Controller Register Overview
DMA Programming for Data Transfer
Simple Mode Programming
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Scatter Gather Mode Programming
Linear Mode Use Case
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Linked List Mode Use Case
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7
Interrupt Handling
DMA Programming Model for FCI
Implementation Notes
FCI Attached to the SRC
DMA Channel Reading from a Flow Controlling the PL Slave
DMA Channel Writing to a Flow Controlling the PL Slave
Programming Model for Changing DMA Channel States
Channel Enabled
Channel Disabled
Channel Paused
Coming Out of Pause
Security
Error Conditions
Software Programing Error
Total Transferred Bytes Overflow
DMA Implements Interrupt Accounting Support
AXI Errors
CAN Controller
Introduction
Features
Functional Description
Block Diagram
Clocks
LPD_LSBUS_CLK Clock
Reference Clock
Example: Configure and Route Internal Clock for Reference Clock
Programming Example – Assign MIO Pin as CAN Reference Clock Input
Resets
Example: Reset using Local CAN Reset
Example: Reset using Reset Subsystem
Configuration Registers
Transmit and Receive Messages
TX High Priority Buffer
Acceptance Filters
Controller Modes
Configuration Mode
Normal Mode
Sleep Mode
Loopback Mode (Diagnostics)
Snoop Mode (Diagnostics)
Mode Transitions
Message Format
Bit Field Details
Writes
Reads
Message Buffering
RX Messages
TX Messages
Reads from RXFIFO
RX and TX Error Counters
Interrupts
List of Interrupts
RXFIFO and TXFIFO Interrupts
Example: Program RXFIFO Watermark Interrupt (12)
Example: Program TXFIFO Watermark Interrupt (13)
Example: Program TXFIFO Empty Interrupt (14)
RX Message Filtering
Acceptance Filter Enable
Acceptance Filter Mask Register
Acceptance Filter Identifier
Example: Program Acceptance Filter
Program the AFMR and AFIR Registers
Example: Program the AFMR and AFIR for Standard Frames
Example: Program the AFMR and AFIR for Extended Frames
Protocol Engine
RX/TX Bit Timing Logic
Time Quanta Clock
Bitstream Processor
CAN0-to-CAN1 Connection
I/O Interface
MIO Programming
Programming Example – Assign MIO Pin to CAN RX Input
Programming Example – Assign MIO Pin to CAN TX Output
MIO-EMIO Signals
Register Overview
Programming Model
Flowchart
Programming Guide Overview
Configuration Mode State
Start-up Controller
Example: Start-up Sequence
Change Operating Mode
Example: Normal to Sleep Mode
Example: Configuration to Sleep Mode
Write Messages to TXFIFO
Example: Write Message to TXFIFO Using Polling Method
Example: Write Message to TXFIFO Using Interrupt Method
Write Messages to TXHPB
Example: Write Message to TXHPB
Read Messages from RXFIFO
Example: Read Message from RXFIFO Using Polling Method
Example: Read Message from RXFIFO Using Interrupt Method
UART Controller
Introduction
Features
UART Controller Functional Description
UART Controller Block Diagram
Control Logic
Baud Rate Generator
Transmit FIFO
Transmitter Data Stream
Receiver FIFO
Receiver Data Capture
Receiver Parity Error
Receiver Framing Error
Receiver Overflow Error
Receiver Timeout Mechanism
I/O Mode Switch
Normal Mode
Automatic Echo Mode
Local Loopback Mode
Remote Loopback Mode
UART0-to-UART1 Connection
Status and Interrupts
Interrupt and Status Registers
Interrupt Mask Register
Channel Status
Non-FIFO Interrupts
FIFO Interrupts
Modem Control
UART Controller Register Overview
Clocks
LSBUS Clock
Reference Clock
Resets
MIO – EMIO Signals
UART Controller Programming Model
UART Controller Programming
I2C Controllers
Introduction
I2C Controller Features
Functional Description
System Block Diagram
I2C Module Block Diagram
I2C Master Mode
Slave Monitoring
10-bit Addressing Mode
I2C Slave Mode
Glitch Filter
I/O Signals
I2C0-to-I2C1 Loopback Connection
Register Overview
Interrupt Mask Register
Interrupt Enable Register
Programming Model
Reset Controller
Configure I/O Signal Routing
Configure Clocks
Controller Configuration
Configure Interrupts
Initiate Data Transfers
Master Read Using Polled Method
Master Read Using Interrupt Method
Master Write Using Interrupt Method
Slave Monitor Mode
I2C Controller Programming Sequence
I2C Controller Programming Steps
SPI Controller
Introduction
Features
Functional Description
FIFOs
RXFIFO
TXFIFO
Clocks
Master Mode SCLK
Slave Mode SCLK
Resets
SPI Controller Modes of Operation
Master Mode
Multi-master Mode
SPI Data Transfers
Data Transfer
Auto/Manual Slave Select and Start
Manual Start
Enable
Command
Clocking
Word Detection
MIO-EMIO Signals
MIO Signals
EMIO Signals
SPI0-to-SPI1 Loopback Connection
Register Overview
Programming Model
Quad-SPI Controllers
Introduction
Legacy Quad-SPI Controller Mode
Linear Address Mode
Generic Quad-SPI Controller Modes
I/O Mode
DMA Mode
SPI Mode
Architecture Overview
System Control
Controller Selection
Legacy Controller to Generic Quad-SPI Controller
Generic Quad-SPI Controller to Legacy Controller
Clock Polarity, Phase, and Baud Rate Reconfiguration
Dynamic Mode and Baud Rate Change Limitations
Reference Clock Change Limitations
Clocks and Resets
Reference Clock and Quad-SPI Interface Clocks
Quad-SPI Feedback Clock
Resets
Generic Quad-SPI Controller
Controller Features
Block Diagram
DMA–AXI Master
SPI Interface Logic
Register Set
APB Interface
Command Generator
RXFIFO
Generic Command FIFO—20-bit Width and 32-bit Depth
Generic Quad-SPI Commands
Generic Controller I/O Wiring Diagrams
Legacy Quad-SPI Controller
Features
System-level View
Address Map and Device Matching For Linear Address Mode
Legacy Quad-SPI Operating Restrictions
Legacy Quad-SPI Functional Description
Legacy Quad-SPI Linear Address Mode
Linear Address Mode AXI Interface Operation
Legacy Quad-SPI AXI Read Command Processing
Legacy Quad-SPI AXI Interface Configuration and Read Modes
Legacy Quad-SPI Controller Unsupported Devices
4-byte Address Support
3-Byte Address Support
Legacy Linear Addressing
Programming Requirements for Linear Mode
Legacy Quad-SPI I/O Interface
Legacy Quad-SPI Single Slave Select 4-bit I/O
Legacy Quad-SPI Dual Slave Select 8-bit Parallel I/O
Legacy Quad-SPI Dual Slave Select 4-bit Stacked I/O
Register Overview
Quad-SPI Tap Delay Values
Programming and Usage Considerations
DMA Mode Configuration Sequence
Transfer Size Limitations
Generic Quad-SPI Controller Programming
Generic FIFO Programming
Programming SPI Modes
Programming Data Transfer Length and Usage of Exponent
Programming Poll
Use Case: Check Success of Page Program/Erase
Terminating Poll
Programming Stripe
Transferring Odd Bytes
Modes of Operation
Generic Quad-SPI Controller in PIO Mode
Generic Quad-SPI Controller in DMA Mode
Flash Commands
NOR Flash Commands
Page Read Command
Quad I/O Read Command
Quad Page Program Command
Two SPI Flash Memories with Separate Buses (Dual Parallel)
Data Arrangement
Two SPI Flash Memories with a Shared Bus (Stacked)
Write Protect
Controller Hold Signal
Controller Interrupt
Programming Examples
Legacy Quad-SPI Controller Programming
Linear Addressing Mode (Memory Reads)
MIO Signals
NAND Memory Controller
Introduction
Features
Functional Description
NAND Flash Interface
Dual-port RAM
ECC
Control Registers
AXI Interface
AXI Master Interface
AXI Slave Interface
Address Aliasing
Register Overview
Clocks and Resets
LSBUS Clock
Reference Clock
Resets
I/O Signal Pins
Programming Model
Flash Initialization
Reset the Target Device (ONFI Reset)
Read ONFI ID
Read ONFI Parameters Page
Change Read Column
XNandPsu_SetEccAddrSize
Erase Block
Read Status
Program Page
Read Page
Change Timing Mode for SDR and NV-DDR
ONFI Set Feature
SD/SDIO/eMMC Controller
Introduction
Features
System/Host Interfaces
SD/SDIO Card Interface
eMMC Card Interface
FIFO Buffer
Speed Modes
Functional Description
Host Interface (Master/Slave)
Register Set
PIO/DMA Controller
Block Buffer
Card Detect
Timeout Control
Command Controller
SD Transmit Control
SD Receive Control
Clocks and Resets
Resets
Clocking Overview
Reference Clock
Tuning Unit
Interface Controller
RX Clock Delay Unit
TXCLK Delay Unit
Controller Clocking
Non-DLL Clock Mode
DLL Clock Mode
Transmit CMD/DAT Delay
Receive Clock Tap Delay
SD Tap Delay Settings
SD Interface Voltage Translation
I/O Signals
MIO-EMIO Signals
Register Overview
SD Command Generation
Programming Examples
DMA Data Transaction
DMA Read Transfer
DMA Write Transfer
SD Configuration
SD Card Initialize
SD CMD Transfer
SD Set Block Size
Setup ADMA2 Descriptor Table
SD Read Polled
SD Write Polled
SD Select Card
eMMC Card Initialize
SD Get Bus Width
SD Change Bus Width
SD Get Bus Speed
SD Change Bus Speed
SD Send Pullup Command
Get eMMC EXT CSD
Resetting the DLL
Manual Tuning
SD/eMMC Example Flow Diagram
Sequence Flowchart for Using DMA
Non-DMA Data Transaction
Steps for a Non-DMA Data Transaction
Non-DMA Write Transfer
Non-DMA Read Transfer
Wait for Buffer Read Ready Interrupt
Sequence Flowchart for Not Using DMA
General Purpose I/O
Introduction
Features
SDK and Hardware Design
Functional Description
MIO Pin Configuration
Basic GPIO Functions
GPIO Channel Architecture
Device Pin Channels
MIO Signals
Input Mode
Output Mode
EMIO Signals
Interrupt Function
System Interfaces
Clock
Reset
Register Overview
MIO Signals
Programming Model
Initialize the GPIO Driver
Run Self-Test on the GPIO
Setup Direction for Bank 0 as Inputs
Setup Direction for Bank 1 as GPIO Outputs and Configure Output Enable
Setup Interrupts for Bank 0 GPIO Inputs
Wait for Interrupts from all the GPIO Inputs to Exit
Multiplexed I/O
Introduction
Overview of the Blocks Function
PS and PL Pins
Output Multiplexer
Master 3-state Enables
Default Logic Levels
MIO Pin Assignment Considerations
Interface Frequencies
I/O Buffer Output Enable Control
Boot from SD Card
eMMC Mapping
Quad-SPI Interface
Drive Strength
MIO Table at a Glance
Register Overview
Programming Model
I2C Interface Programming Example
PS-GTR Transceivers
Introduction
Features
Functionality
Clocking
Power
PCIe v2.0 PHY Protocol
USB3.0 PHY Protocol
DisplayPort 1.2a PHY Protocol (Transmitter only)
Gigabit Ethernet PHY Interfaces
SATA v3.1 PHY Protocol
Functional Description
Interconnect Matrix
Physical Coding Sublayer
Transmit Path
Receive Path
Reference Clock Network
Physical Medium Attachment Sublayer
PLL Lock Status
PMA Transmitter
Serializer and Clock Divider
TX Polarity Control
Data Selection Multiplexer, Predriver, and Voltage Mode Driver
TX Configurable Driver
Electrical Idle
Spread-Spectrum Clocking Transmitter Support
PMA Receiver
Receiver Equalizer
Spread-Spectrum Clocking Receiver
Sampler and Realign
Clock Processor
Phase Interpolator
RX Polarity Control
CDRLF, Deserializer, and PI Controller
EyeScan Module
Sideband Receive Path
Signal Detect
LFPS Detect
Register Overview
PS-GTR Registers
Configuration Program
PCI Express Controller
Introduction
Features
Functional Description
Clock Scheme
Reset Scheme
Integrated Block for PCI Express
Configuration Control (APB Interface)
Power Management
Programmed Power Management
AXI-PCI Express Bridge
Accessing Bridge Internal Registers
AXI Domain
Integrated Block for PCIe Domain
Address Translation
Enhanced Configuration Access Mechanism
Generation of Type-0 or Type-1 Configuration Transactions
Configuration Request Retry Status
Root Port Received Interrupt and Message Controller
Interrupts
PCIe Bus Interface Interrupts
System Interrupts
Transaction Handling
Ingress Transactions
PCIe to AXI Map
Egress Transactions
AXI-PCIe Transaction Mapping
Endpoint Compliance
Security Features
DMA
Suffice DMA Descriptors
Status Updates
Relationship between SRC-Q and STAS-Q
Relationship between DST-Q and STAD-Q
DMA Channel Flow Control
DMA Error Detection
DMA Error Handling
DMA Operation
Dual-CPU Control
System to Card (Host Memory to EP Memory)
Card to System Flow (EP Memory to Host Memory)
Single CPU Control
System to Card Flow (Host memory to EP)
Card to System Flow (EP to Host Memory)
I/O Signals
MIO Signals
Register Overview
Bridge Core Registers
Address Translation Registers
DMA Channel Control and Status Registers
Programming Topics
Programming the PS-GTR Transceiver
Programming Reset Pin
Programming Controller
Bridge Initialization
Programmed I/O Transfers
Ingress Transfers
Driver on a Zynq UltraScale+ MPSoC Endpoint
Driver on Host System
Egress Transfers
Egress Host Driver
Egress Endpoint Driver
Endpoint Mode DMA Operation
Handshake between Host and AXI-CPU Driver
Descriptor Setup
Sequence for Enabling DMA Channel
DMA Operation
Descriptor Post-processing
Disabling an Active DMA Channel
USB Controller
Introduction
USB 2.0/3.0 Controller Details
USB Controller Features
PHY Loopback
Data Flow
Data Structure Network
Data Structure Network
Device Context Data Structure
Slot Context Data Structure and State Diagram
Endpoint Context Data Structure and State Diagram
Transfer TRBs
Normal TRB
Control TRB: Setup Stage
Control TRB: Data Stage
Control TRB: Status Stage
ISOC TRB
NoOp TRB
Event TRBs
Transfer Event TRB
Command Completion Event TRB
Port Status Change Event TRB
Bandwidth Request Event TRB
Doorbell Event TRB
Host Controller Event TRB
Device Notification Event TRB
MFINDEX Wrap Event TRB
Command TRB
NoOp Command TRB
Enable Slot Command TRB
Disable Slot Command TRB
Address Device Command TRB
Configure Endpoint Command TRB
Evaluate Context Command TRB
Reset Endpoint Command TRB
Stop Endpoint Command TRB
Set TR Dequeue Pointer Command TRB
Reset Device Command TRB
Force Event Command TRB
Negotiate Bandwidth Command TRB
Set Latency Tolerance Command TRB
Get Port Bandwidth Command TRB
Force Header Command TRB
Other TRBs
Link TRB
Event Data TRB
Programming Guide
Initial Commands to USB Controller
Host Mode Initialization
Device Detection, Enumeration
Device Detach
Device Programming
Register Overview
SATA Controller
Introduction
Features
Functional Description
System Viewpoint
Description
Command Layer
Local Port Context Management
Vendor Specific BIST Operation
Transport Layer
Link Layer
PHY Control Layer
TrustZone Support
AXI Master Port Security Features
AXI Slave Port Security Features
SATA Clocking and Reset
Register Overview
Programming Considerations
SATA Clock Programming
SATA AXI Bus Configuration
PS-GTR Configuration
PHY Configuration
AHCI SATA Configuration
Issuing Command
Basic Steps When Building a Command
Command FIS (CFIS)
FIS Types
FIS Type Values
DisplayPort Controller
Introduction
Features
System Viewpoint
Functional Description
Video/Graphics
Video Input Stage
Non-live Video/Graphics Input
Live Video/Graphics Input
Audio/Video Buffer Manager
Live Presentation Mode
Non-Live Presentation Mode
Mixed Presentation Mode
Video Rendering Pipeline
Chroma Re-sampling
Alpha Blending
Chroma Keying
Video/Graphics Output Stage
DisplayPort Source Controller
Live Video Output
Live Video Interface
Video Timing Generation
High Level Address Decoder
Video Formats
Live Video Format
Video Packer Format
Graphics Packer Format
Supported Video Formats
Audio
Audio Input Stage
Audio Non-live Input
Audio Live Input
Audio Processing Stage
Audio Mixer
Audio Output Stage
Audio Output Stage from the DisplayPort Source Controller
Audio Live Output
PS-PL Audio Interface
Non-Live Audio Format
Live Audio Format
Audio Metadata
DisplayPort DMA
Descriptor Fields
PREAMBLE Field
EN_DSCR_DONE_INTR Field
EN_DSCR_UP Field
IGNR_DONE Field
BURST_TYPE Field
ARCACHE Field
ARPROT Field
MODE Field
LAST_DSCR Field
LAST DSCR OF FRAME Field
EN_CRC_CHK Field
DONE Field
TIME_STAMP_LSB and TIME_STAMP_MSB Fields
XFER_SIZE Field
LINE_SIZE Field
STRIDE Field
ADDR_EXT Field
Descriptor Identifier Fields
CRC Field
DisplayPort Controller Clocking
PS-PL Clocking Interface
Register Overview
Programming Considerations
Source Controller Setup and Initialization
Source Controller Setup
To change the PS-GTR link rate dynamically (Table: PS-GTR Link Rate):
Upon HPD Assertion
Training Pattern 1 Procedure (Clock Recovery)
Training Pattern 2 Procedure (Symbol Recovery, Interlane Alignment)
Enabling Main Link Video
Accessing the Link Partner
Audio Management
Programming the DisplayPort Source
Reprogramming Source Audio
Info Packet Management
Extension Packet Management
AUX Write Transaction
AUX Read Transaction
Commanded I2C Transactions
Handling I2C Read Defers/Timeout
Handling I2C Write Partial ACK
Handling I2C Write Defer/Timeout
Setting Up a DisplayPort System
AV Buffer Manager Sequence
AV Buffer Manager Programming Options
Key Points to Note in Programming
Retrigger
MIO-EMIO Signals
GEM Ethernet
Introduction
GEM Features
Ethernet Controller Block Diagram
System Viewpoint
Clock Domains
Functional Description
10/100/1000 Operation
SGMII, 1000BASE-SX, or 1000BASE-LX
Rx and Tx FIFO Interfaces to PL
FIFO Interface to PL
Interface Descriptions
FIFO Interface Timing Criteria
MDIO Interface
MAC Transmitter
MAC Receiver
MAC Filtering
Broadcast Address
Hash Addressing
Copy All Frames (or Promiscuous Mode)
Disable Copy of Pause Frames
VLAN Support
Wake-on-LAN Support
DMA Controller
Packet Buffer DMA
AXI Bus Master
RX Buffers
TX Buffers
DMA Bursting on the AXI
DMA Packet Buffer
TX Packet Buffer
RX Packet Buffer
Checksum Offloading
RX Checksum Offload
TX Checksum Offload
IEEE Std 1588 Time Stamp Unit
MAC 802.3 Pause Frame
IEEE Std 802.3 Pause Frame Reception
IEEE Std 802.3 Pause Frame Transmission
MAC PFC Priority-based Pause Frame Support
PFC Pause Frame Reception
I/O Signals
MIO-EMIO Interface Routing
RGMII Interface via MIO
GMII/MII Interface via EMIO
Precision Time Protocol via EMIO
1 PPS signal
MDIO Interface Signals via MIO – EMIO
MAC Loopback
Programming Model
Example: Programming Steps
Initialize the Controller
Priority Queuing
Configure Rx queue pointers
Configure the Controller
I/O Configuration
GEM Ethernet using MIO
GEM Ethernet using EMIO
Configure Clocks
Configure the PHY
Example: PHY Read/Write Operation
Example: PHY Initialization
Configure the Buffer Descriptors
Receive Buffer Descriptor List
Transmit Buffer Descriptor List
Status and Wakeup Interrupts
Example: Configure the Interrupts
Enable the Controller
Transmitting Frames
Example: Transmitting a Frame
TX Queue Sequence
Receiving Frames
Example: Handling a Received Frame
Gigabit Ethernet Debug Guide
Register Overview
Clock Control Register
Control Registers
Status and Statistics Registers
PS-PL AXI Interfaces
Introduction
Block Diagram and Features
Functional Description
FPD-PL Interfaces
PL-PS Interface Specifics
APU Coherent Interfaces
Address Translation and Protection
AXI FIFO Interface
AXI Interface Programming
Additional Per Port HP I/O PL Signals
QoS Priority
Read and Write Data Buffers
Traffic Quality of Service
High Performance PS to PL AXI Interfaces
LPD-PL Interfaces
PL ACE Interface to CCI
A Note About the ACE Protocol
ACE-Lite Interface for I/O Coherency
ACE Interface for Full Coherency
ACP Interface
ACP Limitations
ACP Usage
Choosing a Programmable Logic Interface
APU Perspective
RPU Perspective
FPD and LPD DMAs
PL DMA using the HP and HPC Interfaces
PL Accelerator Block and FPD Interaction
PL Accelerator Block and LPD Interaction
PL DMA via ACP
System Cache using ACE
Signal Overview
PS-PL Interrupts
Processor Event Signals
Register Overview
PL Peripherals
Introduction
PCI Express Integrated
100G Ethernet
DisplayPort Video and Audio Interfaces
Live Video/Graphics Input
Live Video Output
Audio
Audio Live Input
Audio Live Output
Interlaken
GTH and GTY Transceivers
Transmitter
Receiver
Out-of-Band Signaling
PL System Monitor
Video Codec Unit
Video Codec Unit Features
Block Diagram
Video Encoder
Video Decoder
RFSoC
RF Data Converter Subsystem Overview
RF-ADC Features
Soft Decision Forward Error Correction (SD-FEC)
LDPC Decoding/Encoding
Turbo Decoding
Interfaces
PS Clock Subsystem
Introduction
System PLL Clock Units
Clock Generators
Basic Clock Generator Unit
Clock System Overview
Real-time Clock Domain
PMU Clock Domain
Clock Monitor
Glitch-Free Clock Controls
PL Clock Throttle
System PLL Units
PLL Source Clocks
Power Domain Crossing of PLL Clocks
Basic Clock Generators
Interconnect Clock Generators
RPU MPCore Clock Generator
Debug Clock Generators
FPD Debug Clock
LPD Debug Clock
Trace Debug Clock
Timestamp Debug Clock
PL Clock Generators
Programmable Clock PL Throttle
DisplayPort Clock Generators
GPU Clock Generator
SATA Clock Generator
CSU Clock Generators
Special Clock Generators
APU MPCore Clock Generator
DDR Memory Controller Clock Generator
Programming Examples
System PLL Operation
Jitter Considerations
Video Clock Example
Clock Source Programming Example
Integer Multiply and Divide Programming Example
Fractional Multiply and Divide Programming Example
Clock Generator Programming Example
Clock Monitor Programming Example
PLL Integer Divide Helper Data Table
Register Overview
System PLL Control Registers
Clock Generator Control Registers
Reset System
Introduction
Features
Functional Description
POR Reset Sequence
PS_SRST_B Reset Pin During Hardware Boot
Example
System Reset Conditions
Reset Reason Register
PS Only Reset
System-level Software Reset
Debug Reset
PL Reset
PL Configuration Reset
Register Overview
Programming Model
PS-only Reset Sequence
FPD Reset Sequence
RPU Reset Sequence
System Test and Debug
Introduction
Features
JTAG Functional Description
Boundary-Scan
Security
JTAG Security Gates
Toggle Detect on PSJTAG
JTAG Chain Configuration
JTAG Chain Boot States
PJTAG Interface
JTAG Disable
Instruction Register
Instruction Availability
Control Register
Controller Status Register
Error Status Register
PS TAP Controller
PL TAP Controller
Arm DAP Controller
Arm DAP Controller Functionality
External Flash Memory Programming
PS Software Debug
PS-PL Debug
AMD Debug Tools
Third-Party Tool Support
Arm DAP Reset Mechanism
CoreSight Functional Description
CoreSight Environment
Debug Features
System Test and Debug Overview
Debug Definition
Trace Definition
Conventional JTAG Debug (External Debug)
Conventional Monitor Debug (Self-hosted Debug)
Trace Debug
Security
Debug Authentication
Components
JTAG and DAP Overview
Bus Structures
Debug System Control and Access
Debug Access Port
Embedded Cross Trigger
PL to PS and PS to PL Cross Triggering
Trace Sources
APU MPCore Embedded Trace Macrocell
RPU MPCore Embedded Trace Macrocell
System Trace Macrocell
ATB Protocol
PL Fabric Trigger Macrocell
Trace Links
Funnels
Replicator
Trace Sinks
TPIU
TMC
CoreSight Address Map
Clocks, Reset, and Power Domains
JTAG and Debug Clocks
Debug Logic Resets
JTAG Resets
Power
Power-up Request and Acknowledge
Power Domains
JTAG and Debug Logic Power Supplies
I/O Signals
JTAG Interface Signals on MIO
TPIU Data Output on MIO and EMIO
MBIST, LBIST, and Scan Clear (Zeroization)
SEU Occurrences
MBIST
Hardware Boot Process
MBIST Interfaces to System Elements
PMU User Firmware Controls
LBIST
PL Configuration Signals
LBIST Boot Sequence
Scan Clear (Zeroization)
Control Registers
Additional Resources and Legal Notices
Finding Additional Documentation
Documentation Portal
Documentation Navigator
Design Hubs
Support Resources
References
Arm References
PCIe References
Additional References
Please Read: Important Legal Notices
Additional Resources and Legal Notices
Finding Additional Documentation
Documentation Portal
Documentation Navigator
Design Hubs
Support Resources
References
Arm References
PCIe References
Additional References
Please Read: Important Legal Notices