•ECC protection for OCM, PMU-RAM, CSU-RAM, and RPU L1 cache and TCM memories °Address decode error detection °Separate RAMs for ECC syndrome and data °4:1 or greater interleaving of memory cells protected by ECC •Hash validation of CSU BootROM contents at every boot •Lockstep and redundancy covers R5F °R5F lockstep with physical and temporal diversity °Redundant logic in critical control logic such as R5F lockstep checkers •PMU and CSU implemented with redundancy °TMR (triple module redundant) processor cores with physical diversity °Triple redundant flip-flops for critical control bits such as security state •XMPU and XPPU protect memory space •Watch-dog timers °Watchdog timers provided in LPD and FPD °LPD watchdog timers for RPU and PMU