MDIO interface signals routed through the MIO and EMIO are identified in Table: MDIO Interface Signals via MIO and EMIO.
Table 34-17: MDIO Interface Signals via MIO and EMIO
|
MDIO Interface
|
Default Value
|
MIO Pins
|
EMIO Interface Signals
|
|
GEM 0
|
GEM 1
|
GEM 2
|
GEM 3
|
I/O
|
Name
|
Name
|
I/O
|
|
MD clock output
|
~
|
76
|
50,76
|
76
|
76
|
O
|
GEM{0:3}_MDC
|
enet{0:3}_mdio_mdc
|
O
|
|
MD data output
|
~
|
77
|
51,77
|
77
|
77
|
IO
|
GEM{0:3}_MDIO
|
enet{0:3}_mdio_o
|
O
|
|
MD data 3-state
|
~
|
enet{0:3}_mdio_t
|
O
|
|
MD data input
|
0
|
enet{0:3}_mdio_i
|
I
|