An interrupt request signal is asserted if the interrupt is not masked. The following three registers control interrupt signals.
•Write a 1 to IER_{0:1} bits to enable alarm signal (unmask). Write-only.
•Write a 1 to IDR_{0:1} bits to disable alarm signal (mask). Write-only.
•Read the IMR_{0:1} bits to determine the state of the mask (1 means masked). Read-only.