Functional Description

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The reset sequence is a two stage process. The first stage is handled by the reset controller present in the LPD and the second stage is handled by the platform management unit (PMU). The following sections discuss the resets.

This Figure shows how a reset is generated by the two reset controllers; one for each of the power domains (LPD and FPD). The primary device-level reset inputs are from the PS_POR_B and PS_SRST_B device pin, which must be asserted and deasserted based on specific conditions. The Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [Ref 2] contains those specifications. The power-on reset (POR) unit in the PS deasserts the reset signal to the LPD and the FPD clock and reset controllers when the PS power comes up and is stable. The system-level reset signals are controlled using the SLCR registers. The operation of the reset unit requires the PS_REF_CLK to be active.

Figure 38-1:      Top-level Reset Block Diagram

X-Ref Target - Figure 38-1