The write and read eyes should be as wide as possible to provide a stable and robust memory access. The eye position depends upon LCDL, as well as VREF values. The write and read data eye training is used to find out the best eye position by changing LCDL values with an initial calculated and programmed VREF setting.
VREF training is used to determine a range of VREF values where memory interface (write and read) is stable and then determine an optimum write and read eye position.
These types of VREF training are supported:
•DRAM VREF training: this training is used to optimize the write eye by sweeping DRAM VrefDQ values inside memory.
•Host VREF training: this training is used to optimize the read eye by sweeping the PHY I/O's VREF setting.
VREF training completion is signaled by the PGSR0.VDONE bit. If errors are encountered during training, PGSR0.VERR is set. Per byte error flags are visible in DXnGSR3, as listed in Table: DATX8 General Status Register 3 (DXnGSR3).
Table 17-34: DATX8 General Status Register 3 (DXnGSR3)
|
Register
|
Bits
|
Name
|
Description
|
Address
|
|
DX0GSR3
|
[9:8]
|
HVERR
|
Host VREF training error: indicates if set that there is an error in VREF Training of byte 0. Each bit indicates an error for one rank.
|
FD0807EC
|
|
DX1GSR3
|
[9:8]
|
HVERR
|
Same as above, for byte 1.
|
FD0808EC
|
|
DX2GSR3
|
[9:8]
|
HVERR
|
Same as above, for byte 2.
|
FD0809EC
|
|
DX3GSR3
|
[9:8]
|
HVERR
|
Same as above, for byte 3.
|
FD080AEC
|
|
DX4GSR3
|
[9:8]
|
HVERR
|
Same as above, for byte 4.
|
FD080BEC
|
|
DX5GSR3
|
[9:8]
|
HVERR
|
Same as above, for byte 5.
|
FD080CEC
|
|
DX6GSR3
|
[9:8]
|
HVERR
|
Same as above, for byte 6.
|
FD080DEC
|
|
DX7GSR3
|
[9:8]
|
HVERR
|
Same as above, for byte 7.
|
FD080EEC
|
|
DX8GSR3
|
[9:8]
|
HVERR
|
Same as above, for byte 8.
|
FD080FEC
|
|
DX0GSR3
|
[17:16]
|
DVERR
|
DRAM VREF training error: indicates if set that there is an error in VREF Training of byte 0. Each bit indicates an error for one rank.
|
FD0807EC
|
|
DX1GSR3
|
[17:16]
|
DVERR
|
Same as above, for byte 1.
|
FD0808EC
|
|
DX2GSR3
|
[17:16]
|
DVERR
|
Same as above, for byte 2.
|
FD0809EC
|
|
DX3GSR3
|
[17:16]
|
DVERR
|
Same as above, for byte 3.
|
FD080AEC
|
|
DX4GSR3
|
[17:16]
|
DVERR
|
Same as above, for byte 4.
|
FD080BEC
|
|
DX5GSR3
|
[17:16]
|
DVERR
|
Same as above, for byte 5.
|
FD080CEC
|
|
DX6GSR3
|
[17:16]
|
DVERR
|
Same as above, for byte 6.
|
FD080DEC
|
|
DX7GSR3
|
[17:16]
|
DVERR
|
Same as above, for byte 7.
|
FD080EEC
|
|
DX8GSR3
|
[17:16]
|
DVERR
|
Same as above, for byte 8.
|
FD080FEC
|
|
DX0GSR3
|
[26:24]
|
ESTAT
|
VREF training error status code: indicates which phase of error check failed. Valid status encodings are:
ESTAT[0] = Initial VREF check failed.
ESTAT[1] = Final check for DRAM VREF failed.
ESTAT[2] = Final check for Host VREF failed.
|
FD0807EC
|
|
DX1GSR3
|
[26:24]
|
ESTAT
|
Same as above, for byte 1.
|
FD0808EC
|
|
DX2GSR3
|
[26:24]
|
ESTAT
|
Same as above, for byte 2.
|
FD0809EC
|
|
DX3GSR3
|
[26:24]
|
ESTAT
|
Same as above, for byte 3.
|
FD080AEC
|
|
DX4GSR3
|
[26:24]
|
ESTAT
|
Same as above, for byte 4.
|
FD080BEC
|
|
DX5GSR3
|
[26:24]
|
ESTAT
|
Same as above, for byte 5.
|
FD080CEC
|
|
DX6GSR3
|
[26:24]
|
ESTAT
|
Same as above, for byte 6.
|
FD080DEC
|
|
DX7GSR3
|
[26:24]
|
ESTAT
|
Same as above, for byte 7.
|
FD080EEC
|