Trace Debug Clock

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The trace debug clock is controlled by the clk_ctrl_fpd.DBG_TRACE_CTRL register with a single divisor. The clock should be programmed to twice the frequency of the desired trace port clock because it is used to derive the trace port clock. The frequency of trace port clock must be fast enough to allow the trace port to keep up with the amount of data being traced.