The clock generator control registers are divided into the following tables: •AMBA interconnect clocks •Processors, DDR, and DMA clocks •LPD and FPD system clocks •LPD peripheral clocks •FPD peripheral clocks Table 37-5: AMBA Interconnect Clock Control Register Reset Value,Register Set, Address Offset Register Parameter Reset State Pre-FSBL Clock Source Options LPD_LSBUS_CTRL (APB) 0100_1800 h, LPD 0x0AC [SRCSEL]: [DIVISOR0]: [CLKACT]: RPLL. 18 h. Enabled. RPLL, IOPLL, or DPLL_CLK_TO_LPD. IOU_SWITCH_CTRL (AXI LPD) 0000_1500 h, LPD 0x09C [SRCSEL]: [DIVISOR0]: [CLKACT]: RPLL. 15 h. Disabled. RPLL, IOPLL, or DPLL_CLK_TO_LPD. LPD_SWITCH_CTRL (AXI LPD) 0100_0500 h, LPD 0x0A8 [SRCSEL]: [DIVISOR0]: [CLKACT]: RPLL. 05 h. Enabled. RPLL, IOPLL, or DPLL_CLK_TO_LPD. TOPSW_LSBUS_CTRL (APB LPD) 0100_0800 h, FPD 0x0C4 [SRCSEL]: [DIVISOR0]: [CLKACT]: APLL. 08 h. Enabled. APLL, VPLL, DPLL. TOPSW_MAIN_CTRL (AXI FPD) 0100_0400 h, FPD 0x0C0 [SRCSEL]: [DIVISOR0]: [CLKACT]: APLL. 04 h. Enabled. APLL, VPLL, DPLL. Table 37-6: Processors, DDR, and DMA Clock Control Control Register Reset Value,Register Set,Address Offset Register Parameter Reset State Pre-FSBL Comments CPU_R5_CTRL(RPU MPCore) 0200_0600 h, 0x090 [SRCSEL] [DIVISOR0] [CLKACT] [CLKACT_CORE] RPLL. 06 h. Enabled. Enabled. ACPU_CTRL(APU MPCore) 0300_0400 h, 0x060 [SRCSEL] [DIVISOR0] [CLKACT_FULL] [CLKACT_HALF] APLL. 04 h. Enabled. Enabled. CSU_PLL_CTRL 0100_1500 h, 0x0A0 [SRCSEL] [DIVISOR0] [CLKACT] IOPLL. 15 h. Enabled. DDR_CTRL 0100_0500 h, 0x0A0 [SRCSEL] [DIVISOR0] DPLL. 05 h. FPD_DMA_REF_CTRL 0100_0500 h, 0x0B8 [SRCSEL] [DIVISOR0] [CLKACT] APLL. 05 h. Enabled. LPD_DMA_REF_CTRL 0000_2000 h, 0x0B8 [SRCSEL] [DIVISOR0] [CLKACT] RPLL. 20 h. Disabled. Table 37-7: System Clock Control Register Name Reset Value,Address Offset Register Parameter Reset State Pre-FSBL Comments DBG_LPD_CTRL 0100_2000h, LPD 0x068 [SRCSEL] [DIVISOR0] [CLKACT] RPLL. 020 h. Enabled. DBG_FPD_CTRL 0100_2500 h, FPD 0x068 [SRCSEL] [DIVISOR0] [CLKACT] IOPLL_TO_FPD. 025 h. Enabled. DBG_TRACE_CTRL 0000_2500 h, FPD 0x064 [SRCSEL] [DIVISOR0] [CLKACT] IOPLL_TO_FPD. 025 h. Clock stop. DBG_TSTMP_CTRL (Timestamp) 0000_0A00 h, FPD 0x0F8 [SRCSEL] [DIVISOR0] IOPLL_TO_FPD. 0A h. The clock enable is controlled by DBG_FPD_CTRL [CLKACT]. AMS_REF_CTRL (PS SYSMON unit) 0100_1800 h, LPD 0x108 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] RPLL. 18 h. 0 h. Enabled. DLL_REF_CTRL 0000_0000h, LPD 0x104 [SRCSEL] IOPLL. PCAP_CTRL 0000_1500 h, LPD 0x0A4 [SRCSEL] [DIVISOR0] [CLKACT] IOPLL. 15 h. Disabled. TIMESTAMP_REF_CTRL 0000_1800 h, LPD 0x128 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 18 h. 0 h. Disabled. PL{0:3}_REF_CTR 0005_2000 h, LPD 0x0C0 to 0x0CC [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 20 h. 25 h. Disabled. Table 37-8: LPD Peripheral Clock Control Register Name Reset Value,Address Offset Register Parameter Reset State Pre-FSBL Comments GEM{0:3}_REF_CTRL 0000_2500 h, 0x050 - 0x05C [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] [RX_CLKACT] IOPLL. 25 h. 00 h. Disabled. Disabled. GEM_TSU_REF_CTRL 0005_1000 h, 0x100 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 10 h. 05 h. Disabled. USB{0,1}_BUS_REF_CTRL 0005_2000 h, 0x060 -0x064 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 20 h. 05 h. Disabled. UART{0,1}_REF_CTRL 0100_1800 h, 0x074, 0x078 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 18 h. 00 h. Enabled. Same. N/A SPI{0, 1}_REF_CTRL 0100_1800 h, 0x07C, 0x080 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 18 h. 00 h. Enabled. Same. N/A QSPI_REF_CTRL 0100_0800 h, 0x068 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 08 h. 00 h. Enabled. Same. 0F h. 01 h. Same. Quad-SPI boot: CBR: 0101_0F00 h. NAND_REF_CTRL 0005_2000 h, 0x0B4 [SRCSEL][DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 20 h. 05 h. Disabled. Same. h. h. Same. NAND boot: CBR: h. SDIO{0, 1}_REF_CTRL 0100_0F00 h, 0x06C, 0x070 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 0F h. 00 h. Enabled. Same. 19h. 01 h. Same. SD card boot: CBR: 0101_1900 h. CAN{0, 1}_REF_CTRL 0100_1800 h, 0x084, 0x088 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 18 h. 00 h. Enabled. Same. 32 h. 00 h. Same POR reset: PMU: 0100_3200 h. I2C{0, 1}_REF_CTRL 0100_0500 h, 0x120, 0x124 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] IOPLL. 05 h. 00 h. Enabled. Same. N/A Table 37-9: FPD Peripheral Clock Control Register Name Reset Value,Address Offset Register Parameter Reset State Pre-FSBL Comments DP_VIDEO_REF_CTRL 0103_2300 h, 0x070 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] DPLL. 23 h. 0 h. Enabled. DP_AUDIO_REF_CTRL 0103_2300 h, 0x074 [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] VPLL. 23 h. 0 h. Enabled. DP_STC_REF_CTRL 0120_3200 h, 0x07C [SRCSEL] [DIVISOR0] [DIVISOR1] [CLKACT] VPLL. 32 h. 20 h. Enabled. DPDMA_REF_CTRL 0100_0500 h, 0x0BC [SRCSEL] [DIVISOR0] [CLKACT] APLL. 05 h. Enabled. GPU_REF_CTRL 0000_1500 h, 0x084 [SRCSEL] [DIVISOR0] [CLKACT] [PP0_CLKACT] [PP1_CLKACT] IOPLL_TO_FPD. 15 h. Disabled. Disabled. Disabled. PCIE_REF_CTRL 0000_1500 h, 0x0B4 [SRCSEL] [DIVISOR0] [CLKACT] IOPLL_TO_FPD. 15 h. Disabled. SATA_REF_CTRL 0100_1600 h, 0x0A0 [SRCSEL][DIVISOR0] [CLKACT] IOPLL_TO_FPD. 16 h. Enabled.