The BBRAM key memory space is 288-bits. The BBRAM can be programmed by system software running on an RPU or APU processor, or via the PJTAG interface on MIO that connects to the Arm DAP controller and becomes an AXI bus master. The BBRAM block diagram is shown in This Figure. The BBRAM and eFUSE programming details are described in the Programming BBRAM and eFUSEs Application Note (XAPP1319) [Ref 20].
