The poll operation termination is controlled using the POLL_TIMEOUT register and the EN_POLL_TIMEOUT field of the generic Quad-SPI configuration register.
When the EN_POLL_TIMEOUT field is set to 0, the generic Quad-SPI controller polls indefinitely until it matches with the value programmed in the POLL_DATA field of the poll register. In this case, the poll operation is only terminated when the received data matches with the value of the POLL_DATA field. This depends on the poll mask value, if enabled.
When the EN_POLL_TIMEOUT field is set to 1, the value of the POLL_TIMEOUT register is used. The generic Quad-SPI controller increments an internal counter and keeps polling for the number of reference clock cycles configured in the POLL_TIMEOUT register. When the internal counter expires, the generic Quad-SPI controller generates a Poll_Timeout_Int interrupt.
When both upper and lower data buses are active, the interrupt indicates if the captured data of any one or both of the devices captured data does not matched with the POLL_DATA field of the poll register. This depends on the poll mask value, if enabled.
When only one data bus is active, in dual-parallel mode, the poll counter expires when either the lower or upper data is not as expected in the POLL_DATA field of the poll register. This depends on the poll mask value, if enabled.