•Memory mapped configuration, and control registers.
•PS-GTR transceiver registers are exclusively programmed through PCW.
•Independent PS-GTR protocol support per lane (programmable through PCW).
•D+/D- lane polarity inversion for flexible board integration.
•SSC support.
•Elastic buffer management.
•8b10b support for USB3.0 and PCIe v2.0 only. For other protocols, 8b10b support is in the MAC IP.