1.Turn off scrambling and set training pattern 1 in the source through direct register writes. See Table: Clock Recovery.
°SCRAMBLING_DISABLE = 0x01
°TRAINING_PATTERN_SET = 0x01
2.Turn off scrambling and set training pattern 1 in the sink DPCD (0x00102–0x00106) through the AUX channel.
3.Wait 100 µs before reading status registers for all active lanes (0x00202–0x00203) through the AUX channel.
4.If clock recovery failed, check for voltage swing or pre-emphasis level increase requests (0x00206–0x00207) and react accordingly. Run this loop up to five times. If after five iterations this has not succeeded, reduce the link speed, if at a high speed and try again. If already at a low speed, training fails.