|
Task
|
Register
|
Register Field
|
Register Offset
|
Bits
|
Value (Binary)
|
|
Program command for read page (0x3000) with ECC, DMA enabled.
|
Command_Register
|
All
|
0x0C
|
31:0
|
Program the command with required address cycles.
|
|
If DMA is enabled, enable DMA boundary interrupt.
|
Interrupt_Status_Enable_Register
|
dma_int_sts_en | trans_comp_sts_en
|
0x014
|
6 and 2
|
0x44 (hex)
|
|
Else enable buffer read ready interrupt.
|
Interrupt_Status_Enable_Register
|
buff_rd_rdy_sts_en
|
0x014
|
1
|
1b'1
|
|
Enable single bit error and multi-bit error if hardware ECC is enabled.
|
Interrupt_Status_Enable_Register
|
err_intrpt_sts_en | mul_bit_err_sts_en
|
0x014
|
4:3
|
2b'3
|
|
Set page size.
|
Command_Register
|
page_size
|
0x0C
|
25:23
|
3'd0 - 512B
3'd1 - 2 KB
3'd2 - 4 KB
3'd3 - 8 KB
3'd4 - 16 KB
3'd5 - 1 KB 0x16 bit flash support
6-7 - RES
|
|
Program column, page, and block address (next two steps).
|
|
Program memory address register 1.
|
Memory_Address_Register1
|
All
|
0x04
|
31:0
|
•Program block address in bits 31:25.
•Program page address in bits 22:16.
•Program column address in bits 12:0.
|
|
Program memory address register 2.
|
Memory_Address_Register2
|
All
|
0x008
|
31:0
|
Write required values for memory address.
|
|
Select packet size and count.
|
Packet_Register
|
Packet_count | packet_size
|
0x00
|
23:0
|
Required packet size and count.
|
|
If DMA enabled, program DMA system address and buffer boundary (following three steps).
|
|
Invalidate the data cache.
|
|
For 64-bit architecture, program higher address word.
|
DMA_system_address1_register
|
DMA_system_address1
_register
|
0x024
|
31:0
|
Program higher address word.
|
|
Program lower address word.
|
DMA_system_address0_register
|
DMA_system_address0
_register
|
0x50
|
31:0
|
Program lower address word.
|
|
Select the device.
|
Memory_Address_Register2
|
Chip_Select
|
0x08
|
31:30
|
Targets chip select value.
|
|
Set ECC spare command (0X85) if hardware ECC enabled.
|
ECC_Spare_Command_Register
|
Number_of_ECC_and_
Spare_Address_cycles | ECC_Spare_cmd
|
0x3c
|
30:0
|
0X85 for spare command and required address cycles.
|
|
Set page program in program register.
|
Program_Register
|
Read
|
0x10
|
0
|
1b'1
|
|
For non-DMA Mode, perform following steps until all packets received (next six steps).
|
|
Poll for buffer read ready event.
|
Interrupt_Status_Register
|
buff_rd_rdy_reg
|
0x1C
|
1
|
Wait until bit is set or wait time is over.
|
|
If buffer read ready events are equal to packet count, then enable the transmit complete interrupt after transfer completed.
|
Interrupt_Status_Enable_Register
|
trans_comp_sts_en
|
0x014
|
2
|
1b'1
|
|
Else, clear buffer read ready interrupt in status enable register.
|
Interrupt_Status_Register
|
buff_rd_rdy_sts_en
|
0x14
|
1
|
1b'0
|
|
Clear buffer read ready interrupt.
|
Interrupt_Status_Register
|
buff_rd_rdy_reg
|
0x1C
|
1
|
1b'1
|
|
Read packet data.
|
Buffer_Data_Port_Register
|
Data_Port_Register
|
0x030
|
31:0
|
Read until all data received.
|
|
If buffer read ready events are less than packet count, then enable buffer read ready interrupt and start next iteration else break the loop here.
|
Interrupt_Status_Enable_Register
|
buff_rd_rdy_sts_en
|
0x014
|
1
|
1b'1
|
|
Poll for transfer complete event.
|
Interrupt_Status_Register
|
trans_comp_reg
|
0x1C
|
2
|
Wait until transfer is completed or wait time is over.
|
|
Clear the transmit complete interrupt after transfer completed.
|
Interrupt_Status_Enable_Register
|
trans_comp_sts_en
|
0x014
|
2
|
1b'0
|
|
Clear the transmit complete flag after transfer completed.
|
Interrupt_Status_Register
|
trans_comp_reg
|
0x1C
|
2
|
1b'1
|
|
If hardware ECC mode is enabled, check for ECC errors.
|
|
Hamming multi-bit errors
|
|
Read interrupt status.
|
Interrupt_Status_Register
|
mul_bit_err_reg
|
0x1C
|
3
|
Read
|
|
If multi-bit error bit set, clear the status.
|
Interrupt_Status_Register
|
mul_bit_err_reg
|
0x1C
|
3
|
1b'1
|
|
Read ECC error count.
|
ECC_Error_Count_Register
|
Page_bound_Err_count
|
0x38
|
16:8
|
Read
|
|
Hamming single-bit or BCH errors
|
|
Read interrupt status.
|
Interrupt_Status_Register
|
err_intrpt_reg
|
0x1C
|
4
|
Read
|
|
If multi-bit error bit set, clear the status.
|
Interrupt_Status_Register
|
err_intrpt_reg
|
0x1C
|
4
|
1b'1
|
|
Read ECC error count.
|
ECC_Error_Count_Register
|
Page_bound_Err_count
|
0x38
|
16:8
|
Read
|