Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
Release Date
2.4 English

The RX and TX FIFOs are each 128-bytes deep. Software reads and writes these FIFOs using the register mapped data-port registers. The FIFOs bridge two clock domains; the APB interface (LPD_LSBUS_CLK) and the controller's SPI_REF_CLK. Software writes to the TXFIFO in the APB clock domain and the controller reads the TXFIFO in the SPI_Ref_Clk domain. The controller fills the RXFIFO in the SPI_Ref_Clk domain and software reads the RXFIFO in the APB clock domain.