•Integer unit implementing the Arm v7-R instruction set.
•Single and double precision FPU with VFPv3 instructions.
•Arm v7-R architecture memory protection unit (MPU).
•64-bit master AXI3 interface for accessing memory and shared peripherals.
•64-bit slave AXI3 interface for DMA access to the TCMs.
•Dynamic branch prediction with a global history buffer and a 4-entry return stack.
•Separate 128KB TCM memory banks with ECC protection for each TCM.
•32KB instruction and data L1 caches with ECC protection.
•Independent Cortex-R5F processors or dual-redundant configuration.
•32-bit master advanced eXtensible interface (AXI) peripheral interface on each processor for direct low-latency device memory type access to the interrupt controller.
•Debug APB interface to a CoreSight™ debug access port (DAP).
•Low interrupt latency and non-maskable fast interrupts.
•Performance monitoring unit.
•Exception handling and memory protection.
•ECC detection/correction on level-1 memories.
•Lock-step (redundant CPU) configuration is available to mitigate random faults in CPU registers and gates.
•Built-in self-test (BIST) to detect random faults in hardware (probably) caused by permanent failure.
•Watchdog to detect both systematic and random failures causing program flow errors.