PLSYSMON Register Set Access - UG1085

The PL SYSMON unit is controlled by the PLSYSMON register set at 0xFFA5_0C00. These registers are also protected by the XPPU and require a valid clock. In addition, the PCAP isolation wall must be disabled to access the PLSYSMON registers and control the PL SYSMON unit. The APB/AXI and DRP parallel ports provide greater bandwidth access to the SYSMON units than the serial ports.

•AMS requirements.

•AMS.MON_STATUS [jtag_locked] bit (good clock).

•APB slave interface (default mode).

°Check the AMS.PL_SYSMON_CONTROL_STATUS [accessible] bit.)

°No SYSMONE4 instantiation.

•PCAP isolation wall disabled.

•JTAG, I2C/PMBus arbitration.

•VCCINT (check the [PL_INIT] bit.)