The PL bitstream contains configuration data for the device's Programmable Logic (PL). This configuration data can be loaded and read back from the PS using the PCAP interface. The FSBL can handle loading of the initial configuration of the PL using a bitstream stored in the boot image. Alternatively, the PL bitstream can also be loaded at a later time by application code, including using software such as U-Boot or Linux. The XilFPGA software library provides an API that facilitates the loading and read back of configuration data to and from the PL. More information on the XilFPGA library can be found in the Zynq UltraScale+ MPSoC Software Developer’s Guide (UG1137) [Ref 3]. The PL bitstream length and composition depend on the device. Table: Boot Modes lists the attributes and values of the bitstream for device type. Although bitstream options such as compression (BITSTREAM.GENERAL.COMPRESS) can alter the required bitstream length and Since compressed bitstreams can change in size between design iterations, adequate memory should be reserved for the full uncompressed bitstream.
Table 11-10: PL Bitstream Length
|
Device
|
Configuration Bitstream Length
(bits)
|
Minimum Configuration Flash Memory Size
(Mb)
|
Configuration Frames
|
Frame Length in Words
|
Configuration Array Size
in Words
|
Configuration Overhead
in Words
|
|
ZU1
|
23,748,480
|
32
|
7980
|
93
|
742,140
|
515
|
|
ZU2
|
44,549,344
|
64
|
14,964
|
93
|
1,391,652
|
515
|
|
ZU3
|
44,549,344
|
64
|
14,964
|
93
|
1,391,652
|
515
|
|
ZU4
|
61,269,888
|
64
|
20,956
|
93
|
1,948,939
|
515
|
|
ZU5
|
61,269,888
|
64
|
20,956
|
93
|
1,948,939
|
515
|
|
ZU6
|
212,086,240
|
256
|
71,260
|
93
|
6,627,180
|
515
|
|
ZU7
|
154,488,736
|
256
|
51,906
|
93
|
4,827,258
|
515
|
|
ZU9
|
212,086,240
|
256
|
71,260
|
93
|
6,627,180
|
515
|
|
ZU11
|
188,647,264
|
256
|
63,384
|
93
|
5,894,712
|
515
|
|
ZU15
|
229,605,952
|
256
|
77,147
|
93
|
7,174,671
|
515
|
|
ZU17
|
290,744,896
|
512
|
97,691
|
93
|
9,085,263
|
515
|
|
ZU19
|
290,744,896
|
512
|
97,691
|
93
|
9,085,263
|
515
|
|
ZU21
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU25
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU27
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU28
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU29
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU39
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU42
|
166,864,320
|
256
|
56070
|
93
|
5,214,510
|
515
|
|
ZU43
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU46
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU47
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU48
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU49
|
275,498,848
|
512
|
92,568
|
93
|
8,608,824
|
515
|
|
ZU63
|
166,864,320
|
256
|
56070
|
93
|
5,214,510
|
515
|
|
ZU64
|
166,864,320
|
256
|
56070
|
93
|
5,214,510
|
515
|
|
ZU65
|
166,864,320
|
256
|
56070
|
93
|
5,214,510
|
515
|
|
ZU67
|
166,864,320
|
256
|
56070
|
93
|
5,214,510
|
515
|
|
ZU3T
|
41,665,600
|
64
|
13,995
|
93
|
1,301,535
|
515
|
Note: Compressed bitstreams can be also encrypted and authenticated.
The allowed register accesses depend on the boot mode and are listed in Table: Register Access Range and Boot Mode.
Table 11-11: Register Access Range and Boot Mode
|
Control Register
|
Ranges
|
Secure Boot Mode
|
|
ACPU_GIC
|
0xF9000000 to 0xF900FFFC
|
Yes
|
|
SATA
|
0xFD070000 to 0xFD0C00FC
|
Yes
|
|
PCIE
|
0xFD0E0000 to 0xFD0EFFFC
|
Yes
|
|
CRF_APB
|
0xFD1A0000 to 0xFD1A001C
|
Yes
|
|
CRF_APB
|
0xFD1A0048 to 0xFD1A00F8
|
Yes
|
|
AFIFM_DP
|
0xFD360000 to 0xFD4AFFFC
|
Yes
|
|
APU
|
0xFD5C0000 to 0xFD5CFFFC
|
Yes
|
|
CCI_REG
|
0xFD5E0000 to 0xFD5EFFFC
|
Yes
|
|
FPD_SLCR
|
0xFD610000 to 0xFD61FFFC
|
Yes
|
|
FPD_GPV
|
0xFD6E0000 to 0xFD70FFFC
|
Yes
|
|
IOU_GPV
|
0xFE000000 to 0xFE10FFFC
|
Yes
|
|
LPD_GPV
|
0xFE000000 to 0xFE10FFFC
|
Yes
|
|
DPROM
|
0xFE800000 to 0xFF05FFFC
|
Yes
|
|
SPI
|
0xFE800000 to 0xFF05FFFC
|
Yes
|
|
GPIO
|
0xFF0A0000 to 0xFF0AFFFC
|
Yes
|
|
QSPI
|
0xFF0F0000 to 0xFF0F01FC
|
Yes
|
|
NAND 0
|
0xFF100000 to 0xFF100020
|
Yes
|
|
NAND 1
|
0xFF100028 to 0xFF10004C
|
Yes
|
|
NAND 2
|
0xFF10005C to 0xFF10006C
|
Yes
|
|
TTC1 to TTC4
|
0xFF110000 to 0xFF14FFFC
|
Yes
|
|
SDIO 0
|
0xFF160004 to 0xFF160054
|
Yes
|
|
SDIO 0
|
0xFF160060 to 0xFF160100
|
Yes
|
|
SDIO1
|
0xFF170004 to 0xFF170054
|
Yes
|
|
SDIO1
|
0xFF170060 to 0xFF170100
|
Yes
|
|
IOU_SLCR
|
0xFF180000 to 0xFF18FFFC
|
Yes
|
|
LPD_SLCR
|
0xFF250000 to 0xFF41FFFC
|
Yes
|
|
CRL_APB
|
0xFF5E0000 to 0xFF5E009C
|
Yes
|
|
CRL_APB
|
0xFF5E00A4 to 0xFF5E01DC
|
Yes
|
|
RPU - AFIFM
|
0xFF9A0000 to 0xFF9BFFFC
|
Yes
|
|
APM – RTC
|
0xFFA00000 to 0xFFA6FFFC
|
Yes
|
|
MBISTJTAG
|
0xFFCF0000 to 0xFFCFFFFC
|
Yes
|