A group of approximately 160 shared peripheral interrupts (SPIs) from various modules can be routed to one or both of the CPUs or the PL. The interrupt controller manages the prioritization and reception of these interrupts for the CPUs.
A group of approximately 160 shared peripheral interrupts (SPIs) from various modules can be routed to one or both of the CPUs or the PL. The interrupt controller manages the prioritization and reception of these interrupts for the CPUs.