There are separate private CPU registers for the RPUs and APUs to program the interrupt controllers. The addresses are shown in Table: CPU Private Registers. The APU_GIC is located on the AXI interconnect and can be made exclusively accessible to the APU by using the FPD_XMPU protection unit.
Note: The generic CPU timer, L2 cache, and SCU (etc.) in the APU can only be accessed through co-processor instructions, they are not memory mapped.