Lock-Step Operation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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When the Cortex-R5F processors are configured to operate in the lock configuration, only one set of CPU interfaces are used. Because the Cortex-R5F processor only supports the static split/lock configuration, switching between these modes is only permitted right after the processor group is brought out of reset. The input signals SLCLAMP and SLSPLIT control the mode of the processor group. These signals control the multiplex and clamp logic in the locked configuration. When the Cortex-R5F processors are in the lock-step mode (This Figure), there should be code in the reset handler to ensure that the distributor within the generic interrupt controller (GIC) dispatches interrupts only to CPU0.


IMPORTANT:   During the lock-step operation, the TCMs that are associated with the redundant processor become available to the lock-step processor. The size of each ATCM and BTCM becomes 128 KB with BTCM interleaved accesses from the processor and AXI slave interface.

Figure 4-2:      RPU Cortex-R5 Processor Lock-step Mode

X-Ref Target - Figure 4-2