Transmit CMD/DAT Delay

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The TX CMD/DAT delay is used to delay the CMD/DAT lines to avoid a hold time violation in the card due to board layout timing issues. In some cases, the board layout might not be optimal and the CMD/DAT lines might have hold time violations on the card because the SD_CLK and CMD/DAT are source synchronous for the card.

One option is to use delay buffers on each of the CMD and eight DAT lines to provide enough hold margin and use these delayed outputs to the SD interface. This approach has the disadvantage of using nine delay lines and also not having the same delay on each of the CMD/DAT lines. Another option is to delay the internal sd_clk that is being sent out on the clock line (as SD_CLK), and use this delayed clock to flop out the CMD/DAT lines. This approach has the advantage of using only one single DLL/delay on the clock line and provides uniform output delays across the CMD/DAT lines.

The TX clock delay unit uses the delay buffers or a DLL to generate a phase-shifted clock. Using the variable delay output, you can program the tap delay using the external ports. To configure the OTAPDLYSEL, refer to the Program Sequence for DLL TAP Delay in Table: SD Change Bus Speed. The following are bit fields in SD{0,1}_OTAPDLYSEL.

sd{0,1}_otapdlysel[5:0]: Used to select the optimum delay from 8 to 45 tap delay lines.

The TXFLOPS unit implements the final stage registers using this delayed clock. The TXFLOPS unit also implements two sets of registers for each of the CMD/DAT lines (one for the positive edge output and another one for the negative edge output).

In the case of DDR, both the flip-flops are used and in SDR mode, only the positive edge is used (DS mode uses the negative edge outputs) when operating in default DS. The outputs are driven on the falling edge of the clock so that the card can have enough setup/hold time when latching the data. In this case, the output tap delay control is not necessary and should be disabled.

When operating in HS modes and other SDR modes, the output data is driven on the rising edge of the clock. The same clock is also output to the card (SD interface). Based on the post-silicon board layout, the card might see hold time violations for the CMD/DAT lines. To avoid this, the output tap delay lines can be programmed under user control.