The I/O peripheral registers are accessed through the 32-bit APB bus. The base addresses for both the low-power domain and the and full-power domain peripherals are listed in Table: I/O Peripherals Register Map (LPD) and Table: I/O Peripheral Register Map (FPD).
Base Address |
Description |
---|---|
0xFF00_0000, 0xFF01_0000 |
UART0, UART1 |
0xFF02_0000, xFF03_0000 |
I2C0, I2C1 |
0xFF04_0000, 0xFF05_0000 |
SPI0, SPI1 |
0xFF06_0000, 0xFF07_0000 |
CAN0, CAN1 |
0xFF0A_0000 |
GPIO |
0xFF0B_0000, 0xFF0C_0000, |
GEM0, GEM1, GEM2, GEM3 |
0xFF0F_0000 |
QSPI |
0xFF10_0000 |
|
0xFF16_0000, 0xFF17_0000 |
SD0, SD1 |
0xFF99_0000 |
IPI message buffer memory; see Table: IPI Channel and Message Buffer Default Associations. |
0xFF9D_0000, 0xFF9E_0000 |
USB0, USB1 |
0xFFA5_0000, 0xFFA5_0800, |
System monitor register sets (AMS, PSSYSMON, PLSYSMON) |
0xFFCB_0000 |
CSU_SWDT, system watchdog timer (csu_pmu_wdt). |
Notes: 1.NAND cannot be accessed through AXI as a linear mode peripheral. 2.AXI address cannot be directly translated to NAND memory address. 3.The default address for the PL SYSMON register set is 0xFFA5_0C00, but can be changed by instantiating the SYSMONE4 LogiCORE and mapping it to an M_AXI_HPMx_FPD or M_AXI_HPM0_LPD interface to the PL. |