Table: Debug Logic Resets lists the reset signals generated by the CRL_APB.RST_LPD_DBG register in the PS reset subsystem. Table 39-11: Debug Logic Resets Bit Field Power Domain Description rpu_dbg{0, 1}_reset LPD Reset debug logic in the RPU cores dbg_lpd_reset LPD Reset debug logic in the LPD dbg_fpd_reset FPD Reset debug logic in the FPD