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Register Name
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Register Description
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PORT_TYPE
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Set port type register.
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QOS_CTRL
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Set port type register.
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RD_HPR_THRSLD
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Set value for read high-priority read (HPR) CAM threshold.
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RD_LPR_THRSLD
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Set value for read low-priority read (LPR) CAM threshold.
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WR_THRSLD
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Set value for write CAM threshold.
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ZQCS_CTRL0
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ZQCS control register 0.
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ZQCS_CTRL1
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ZQCS control register 1.
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ZQCS_STATUS
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ZQCS status register.
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DDRC_EXT_REFRESH
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DDRC external refresh control register.
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DDRC_EXT_REFRESH_RANK0_REQ
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DDRC_EXT_REFRESH_RANK1_REQ
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QOS_IRQ_STATUS
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Interrupt status register for intrN. This is a sticky register that holds the value of the interrupt until cleared with a value of 1.
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QOS_IRQ_MASK
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Interrupt mask register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
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QOS_IRQ_ENABLE
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Interrupt enable register. A write of zero to this location unmasks the interrupt. (IMR: 0)
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QOS_IRQ_DISABLE
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Interrupt disable register. A write of one to this location masks the interrupt. (IMR: 1)
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DDRC_URGENT
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DDRC urgent sideband signal control register.
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DDRC_QVN_CTRL
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DDRC QVN control register.
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DDRC_MRR_STATUS
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DDRC MRR register status.
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DDRC_MRR_DATA{0:11}
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DDRC MRR register data {0:11}.
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DDR_CLK_CTRL
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DDR subsystem clock control.
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