CSU Clock Generators

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2023-12-21
Revision
2.4 English

The CSU can be clocked by either the SysOsc or a PLL as selected by the csu_ctrl register (0xFFCA0004). The CSU_PLL_CTRL register (0xFF5E00A0) controls the configuration of the PLL including its source – IOPLL, RPLL, DPLL_CLK_TO_LPD – as well as its 6-bit divider. Refer to the Zynq UltraScale+ Devices Register Reference (UG1087) for further information on these registers.

Note:   

1.The input clock to the CSU block is also referred to as the CSU crypto interface block frequency.

2.The maximum CSU crypto interface block frequency(FCSUCIBMAX) is 400 Mhz ,refer to Table 29 in the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925).

3.When the CSU is clocked by the PLL, this clock is referred to as the CSU_PLL_CLK by other registers like the CHKRx_CTRL registers.