L2 Memory Subsystem

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
Release Date
2.4 English

The Cortex-A53 MPCore processor’s L2 memory system size is 1 MB. It contains the L2 cache pipeline and all logic required to maintain memory coherence between the cores of the cluster. It has the following features:

An SCU that connects the cores to the external memory system through the master memory interface. The SCU maintains data-cache coherency between the APU MPCore and arbitrates L2 requests from the cores.

The L2 cache is 16-way set-associative physically-addressed.

The L2 cache tags are looked up in parallel with the SCU duplicate tags. If both the L2 tag and SCU duplicate tag hit, a read accesses the L2 cache in preference to snooping one of the other processors.