An example Ethernet communications wiring connection is shown in This Figure.
Figure 34-10: Ethernet MIO Wiring Connections
|
X-Ref Target - Figure 34-10
|
All Ethernet I/O pins routed through the MIO are on MIO Bank 1 and Bank 2 (see Table: Ethernet RGMII Interface Signals via MIO Pins).
Table 34-13: Ethernet RGMII Interface Signals via MIO Pins
|
Controller Signal
|
MIO Pins
|
|
Signal Description
|
Default Controller Input Value
|
GEM 0
|
GEM 1
|
GEM 2
|
GEM 3
|
Name
|
I/O
|
|
Tx clock to PHY
|
~
|
26
|
38
|
52
|
64
|
RGMII_TX_CLK
|
O
|
|
Tx control to PHY
|
~
|
31
|
43
|
57
|
69
|
RGMII_TX_CTL
|
O
|
|
Tx data 0 to PHY
|
~
|
27
|
39
|
53
|
65
|
RGMII_TXD[0]
|
O
|
|
Tx data 1 to PHY
|
~
|
28
|
40
|
54
|
66
|
RGMII_TXD[1]
|
O
|
|
Tx data 2 to PHY
|
~
|
29
|
41
|
55
|
67
|
RGMII_TXD[2]
|
O
|
|
Tx data 3 to PHY
|
~
|
30
|
42
|
56
|
68
|
RGMII_TXD[3]
|
O
|
|
Rx clock from PHY
|
0
|
32
|
44
|
58
|
70
|
RGMII_RX_CLK
|
I
|
|
Rx control from PHY
|
0
|
37
|
49
|
63
|
75
|
RGMII_RX_CTL
|
I
|
|
Rx data 0 from PHY
|
0
|
33
|
45
|
59
|
71
|
RGMII_RXD[0]
|
I
|
|
Rx data 1 from PHY
|
0
|
34
|
46
|
60
|
72
|
RGMII_RXD[1]
|
I
|
|
Rx data 2 from PHY
|
0
|
35
|
47
|
61
|
73
|
RGMII_RXD[2]
|
I
|
|
Rx data 3 from PHY
|
0
|
36
|
48
|
62
|
74
|
RGMII_RXD[3]
|
I
|
|
GEM TSU clock options
|
~
|
50,51
|
50,51
|
50,51
|
50,51
|
GEM_TSU_CLK
|
I
|
