Master Mode SCLK

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

In master mode, the I/O signals are clocked by the controller generated SCLK that is derived from the SPI_REF_CLK using the baud-rate divider using the spi.Config [BAUD_RATE_DIV] bit field. The range of the baud-rate divider is from a minimum of 4 to a maximum of 256 in binary steps (i.e., divide by 4, 8, 16,... 256). The slave select input pin must be driven synchronously with respect to the SCLK input.