A sideband signal, AxPOISON, renders an AXI transaction (read or write) invalid and causes an error response (AXI SLVERR). If a write is poisoned, all of its strobes are deasserted, making the write effectively transparent to the memory. If a read is poisoned, the command is issued to the DDR memory and all of the read data beats are overridden and returned as all zeros in conjunction with error response.