Error Handling

Master ID list parity error

The MASTER_IDnn register associated with the parity error is disabled and cannot enable a match, that is, MATCH [nn] is forced to 0. The MID_PARITY bit of the ISR register is set and an interrupt can optionally be signaled.

Master ID list read only error

A master ID read-only error occurs when any matched MASTER_IDnn register is enabled by the corresponding bit of the PERM field from the selected entry for the addressed peripheral, its MIDR bit is set, and the transaction is a write. When multiple master IDs are both matched and enabled and one or more have MIDR bits set, a master ID read-only error is still flagged. The MID_RO bit of the ISR register is set.

Master ID list miss error

When all MATCH vector bits are zero, a master ID miss error occurs. The MID_MISS bit of the ISR register is set.

Aperture permission list parity error

The transaction is disallowed and APER_PARITY bit of the ISR register is set. An interrupt can optionally be signaled.

Transaction TrustZone error⁽²⁾

When a non-secure transaction attempts to access a secure slave, a transaction TrustZone error occurs. This error is flagged only when there is no MID_MISS error and no APER_PARITY error. This error is not flagged when there is a MID_MISS error or an APER_PARITY error. The transaction is poisoned and an interrupt can optionally be signaled.

Transaction permission error⁽²⁾

When a master ID is not allowed to access a slave, a transaction permission error occurs. An access to an address not covered by the XPPU causes this type of error. A burst length/size error (when accessing 32B buffers) also causes this type of error to occur. This error is flagged only when there is no MID_MISS error and no APER_PARITY error. This error is not flagged when there is a MID_MISS error or an APER_PARITY error. The transaction is poisoned. An interrupt can optionally be signaled.

Notes:

1.Access to an address not covered by the aperture permission registers goes through the XPPU intact.

2.The first transaction address, master ID, and read/write mode are captured for debugging. When there are simultaneous read/write errors, only the write error is recorded. Only the first error is recorded. To record further errors, the ISR (interrupt status register) must be cleared first.