Interconnect Matrix

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID

UG1085

Release Date

2023-12-21

Revision

2.4 English

The interconnect matrix (ICM) implements connectivity between the media access controllers (MACs) and the physical coding sublayer (PCS). The ICM is automatically programmed by the Processing System Configuration Wizard (PCW). Table: Interconnect Matrix shows the connectivity implemented by the ICM between PS-GTR transceivers and the available MACs.

Table 29-1: Interconnect Matrix
Controller	PHY Lane 0	PHY Lane 1	PHY Lane 2	PHY Lane 3
PCIe v2.0	PCIe.0	PCIe.1	PCIe.2	PCIe.3
SATA	SATA.0	SATA.1	SATA.0	SATA.1
USB0 3.0	USB0	USB0	USB0
USB1 3.0				USB1
DisplayPort	DP.1	DP.0	DP.1	DP.0
GEM0⁽¹⁾	GEM0
GEM1⁽¹⁾		GEM1
GEM2⁽¹⁾			GEM2
GEM3⁽¹⁾				GEM3
Notes: 1.The GEM Ethernet interface to the GTRs includes SGMII, 1000BASE-SX, and 1000BASE-LX protocols.

PS-GTR transceivers can be broadly divided into the following blocks.

•Physical Coding Sublayer

•Reference Clock Network

•GTR reference clock PS_MGTREFCLKP/N should be stable before releasing the PS_POR_B, just like PS_REF_CLK.