SATA AXI Bus Configuration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)
Document ID
UG1085
Release Date
2023-12-21
Revision
2.4 English
Table 32-5:      Configure SATA AXI Bus

Task

SATA_AHCI_VENDOR Register Set

Bit Field

Register Offset

Bits

Value

Select 64-bit bus width

PAXIC

[ADBW]

0xC0

1:0

2b'01