Table: APU MPCore Power Islands shows the power islands supported by the Cortex-A53 processor.
Table 3-1: APU MPCore Power Islands
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Power Island
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Description
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CORTEXA53
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Includes the SCU, the L2 cache controller, and the debug registers that are described as being in the debug domain. This domain is a part of the PS full-power domain (FPD).
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PDL2
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Includes the L2 cache RAM, L2 tag RAM, L2 victim RAM, and the SCU duplicate tag RAM.
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PDCPU[4]
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This represents core 0, core 1, core 2, and core 3. It includes the advanced SIMD and floating-point extensions, the L1 TLB, L1 cache RAMs, and debug registers.
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