Address Translation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The bridge provides eight fully-configurable address apertures to support address translation both for ingress (from PCIe to AXI) and egress (from AXI to PCIe) transactions.

In an AXI master, up to eight ingress translation regions can be set up. Translation is done for the PCIe TLPs that are not decoded as MSI or MSI-X interrupts or internal DMA transactions.

In an AXI slave, up to eight translation regions can be set up. Translation is done for AXI transactions destined for PCIe and not PCIe ECAM or any other internal bridge register access.


IMPORTANT:   For egress translations, it is important to limit the AXI domain address to the following ranges per the System Address Map.

256 MB region starting at 0xE000_0000.

8 GB region starting at 0x6_0000_0000.

256 GB region starting at 0x80_0000_0000.

Only when AXI transactions target these ranges are they routed to the controller for PCIe for further translation by the bridge.

In the following discussions, the term tran refers to ingress/egress translation. For example, tran_size refers to translation size and a tran_src_base refers to ingress/egress_src_base.

A translation is hit when the following occurs.

Translation is enabled (tran_enable == 1).

The tran_src_base[63:(12+tran_size)] == source address [63:(12+tran_size)].

On a hit, the upper source address bits are replaced with destination base address bits before forwarding the transaction to the destination.

Destination address = {tran_dst_base[63:(12+tran_size)] source address[12+tran_size]}.

If a translation is marked invalid (tran_invalid == 1), the transaction is not forwarded to destination and is handled as error.

For egress, DECERR response is returned on AXI.

For ingress, it is handled as an unsupported request on the PCIe.

If translation is valid (tran_invalid==0) and security_enable==1 then the following occurs.

For ingress, ARPROT/AWPROT on AXI is assigned value from tz_at_ingr[i] associated with the translation.

For egress, if ARPROT/AWPROT from AXI matches the security level of tz_at_egr[i] associated with the translation then transaction is forwarded to PCIe. Otherwise, it is discarded with SLVERR response on AXI.


IMPORTANT:   The security values for translation (tz_at_ingr/egr) are programmed at boot time as part of the SLCR_PCIE register under the FPD_SLCR_SECURE register set in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].

The following sequence provides an example for ingress address translation.

1.Consider host assigns PCIe BAR2 = 0xFFA0_0000; 1MB size.

2.Ingress source base = 0xFFA0_0000; destination base = 0x44A0_0000;
aperture size = 64 KB

3.Incoming PCIe memory transaction hitting BAR2 at 0xFFA0_xyzw translates to address 0x44A0_xyzw on AXI master port.

Note:   The source/destination address programmed should be aligned to the translation aperture size. For a 64 KB aperture size, the lower 16 bits of the source/destination addresses must be zeros.

If multiple translation hits occur, the translation with the lowest index (lowest translation register address offset for the ingress/egress direction) is used for the transaction.

When operating as an Endpoint, the PCIe BARs are setup by the host PC during enumeration and ingress translations required for PCIe to AXI translations are set up by the AXI CPU.


IMPORTANT:   The bridge registers are accessible only through the AXI interface and not over PCIe by default. Host CPU access to bridge registers is enabled by writing to the bridge register (cfg_disable_pcie_bridge_reg_access bit in the AXI_PCIE_MAIN.cfg_pcie_rx0 register) through AXI.

When a transaction fails to hit all translations, the subtractive decode (if enabled) and the transaction is forwarded without translation. This is controlled by the AXIPCIE_MAIN.I_ISUB_CONTROL register for ingress translations and the AXIPCIE_MAIN.E_ESUB_CONTROL register for egress translations.