Task |
SD{0, 1} and IOU_SLCR Registers |
Register Field |
Register Offset |
Bits |
Value |
---|---|---|---|---|---|
For SD card |
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Set block size to desired value. |
reg_blocksize |
xfer_blocksize |
0x04 |
11:0 |
Block size value |
Set up ADMA descriptor table (see Table: Setup ADMA2 Descriptor Table). |
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Set transfer mode with data direction and DMA enable. |
reg_transfermode |
xfermode_dmaenable | xfermode_dataxferdir |
0x0C |
4 and 1 |
0x11 |
Data cache (dcache) invalidate range. |
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Send CMD6. |
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Check for transfer completed. |
reg_normalintrsts |
All |
0x30 |
15 |
Read operation |
Clear the error interrupts (if any). |
reg_errorintrsts |
All |
0x30 |
15:0 |
0xF3FF |
Check transfer complete and clear if transfer is completed. |
reg_normalintrsts |
normalintrsts_xfercomplete |
0x30 |
1 |
1b'1 |
Change clock frequency to 50 MHz (see Table: SD Clock Frequency Change). |
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Enable high speed. |
reg_hostcontrol1 |
hostctrl1_highspeedena |
0x28 |
2 |
1b'1 |
Read response 0. |
reg_response0 |
command_response |
0x10 |
15:0 |
Read |
For eMMC card |
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Send CMD6 with eMMC high-speed argument and wait 2 ms. |
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Change clock frequency to 52 MHz. |
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Enable high speed. |
reg_hostcontrol1 |
hostctrl1_highspeedena |
0x28 |
2 |
1b'1 |
Set block size value. |
reg_blocksize |
xfer_blocksize |
0x04 |
11:0 |
Block size value |
Set the mode to data transfer. |
reg_transfermode |
xfermode_dataxferdir |
0x0C |
4 |
0x10 |
Set the execute tuning mode. |
reg_hostcontrol2 |
hostctrl2_executetuning |
0x3E |
6 |
0x40 |
SD card: send CMD19 or eMMC card: send CMD 21. |
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Check if the reg_hostcontrol2 for tuning mask bit is not set. |
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Repeat the process until the tuning mask bit is not set. |
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Check the sampling clock select is set. |
reg_hostcontrol2 |
hostctrl2_ samplingclkselect |
0x3E |
8 |
0x80 |
Set the desired clock frequency using Table: SD Clock Frequency Change, if sampling clock selection is set. |
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Program sequence for DLL tap delay for SD0 and SD1 controllers for high-speed cards. |
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Set the DLL reset value. |
SD_DLL_CTRL |
SD{0,1}_DLL_RST |
0x0 |
2 and 18 |
0x4 |
Set the ITAPCHGWIN to gate the glitches in the line. |
SD_ITAPDLY |
SD{0,1}_ITAPCHGWIN |
0x0 |
9 and 25 |
0x200 |
Set the ITAPDLYENA. |
SD_ITAPDLY |
SD{0,1}_ITAPDLYENA |
0x0 |
8 and 24 |
0x100 |
Unset the ITAPCHGWIN. |
SD_ITAPDLY |
SD{0,1}_ITAPCHGWIN |
0x0 |
9 and 25 |
Clear bit 9 |
Set the taps for the desired clock value. |
SD_OTAPDLYSEL |
SD{0,1}_OTAPDLYSEL |
0x0 |
5:0 and 21:16 |
Desired value based on the clock. |
Release DLL reset. |
SD_DLL_CTRL |
SD{0,1}_DLL_RST |
0x0 |
2 and 18 |
Clear bit 2. |
Set the taps for the desired clock value. |
SD_OTAPDLYSEL |
SD1_OTAPDLYSEL |
0x0 |
21:16 |
Desired value based on the clock. |
Unset the DLL reset value. |
SD_DLL_CTRL |
SD1_DLL_RST |
0x0 |
18 |
Unset the bit 2. |