AXI Interface Programming

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

An advanced peripheral bus (APB) interface is provided to allow for control and monitoring of the module's functions.

The FIFO interface contains the following features.

8-deep write and read command queue depths.

Read and write command acceptance capability of eight.

The maximum number of outstanding unique IDs issued to the PS is eight per port, per channel.

128 x 128-bit deep read and write data FIFOs.

Programmable release modes for write commands.

Programmable issuing capability per port, per channel, up to a maximum of 16. This is possible only if the limit of eight outstanding IDs is not exceeded and there is space available in the data FIFO.

Command and data FIFO fill-level exported to the programmable logic.

The ability to write to the data FIFO without the writing the corresponding write commands.

Upsizing for full-width, aligned, and unaligned INCR-type bursts.

Dynamic command upsizing translation supported between 32-bit or 64-bit PL interfaces and 128-bit PS-side, controllable with the AxCACHE[1] bit.


TIP:   Upsizing occurs for full-width, INCR burst-type commands when the AxCACHE[1] bit is set. All other command-types are expanded. The process of upsizing involves modification of the AWSIZE field to 128-bit, as well as adapting the AWLEN field appropriately.

Expansion or upsizing can be dynamically controlled, on a per-command basis, based on AxCACHE[1] bit value.

Note:   The write latency (i.e., the time from when the write request is sent to the reception of the BRESP) is dependent on factors such as system load and DDR latency. The FIFO interface sends the write command/data all the way to the destination slave. The slave responds with a BVALID and the BVALID is returned to the FIFO interface and then to the PL. There is no capability for an early BRESP, that is, an early response to the PL from the AFI is not sent, but the DDR controller has the capability to send an early response to the AXI interface.