Flowchart

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID

UG1085

Release Date

2023-12-21

Revision

2.4 English

This Figure shows the programming flowchart. Table: CAN Get Mode through Table: CAN Set Bit Timing list the CAN controller modes.

Figure 20-7: CAN Controller Flowchart
X-Ref Target - Figure 20-7

Table 20-8: CAN Get Mode
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
If CONFIG (bit 0) bit is set, the device is in configuration mode.
If NORMAL (bit 3) bit is set, then if the SNOOP (bit 12) bit is set, then the device is in snoop mode, else device is in normal mode.
When none of these (CONFIG, NORMAL, or SNOOP) bits are set, device is in loopback mode.
Read status register	SR	All	0x18	31:0	Read operation
Notes: 1.If CONFIG (bit 0) bit is set, device is in configuration mode. 2.If NORMAL bit (bit 3) is set, then if SNOOP bit (bit 12) is set, then device is in snoop mode, else device is in normal mode. 3.When none of above bits are set, device is in loopback mode.

Table 20-9: CAN Set Baud Rate and Prescaler
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
Get the current mode of the device to confirm that the device is in configure mode. Refer to the CAN Get Mode.
Program baud rate value.	BRPR	BRP	0x08	7:0	7b'00101001

Table 20-10: CAN Set Bit Timing
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
Get the current mode of the device to confirm the device is in configure mode. Refer to the CAN Get Mode.
Program the baud rate value.	BTR	SJW \| TS2 \| TS1	0x0C	8:0	8b110101111

Table 20-11: CAN Enter Mode
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
To get the current mode of to device. Refer to the CAN Get Mode.
If current mode is normal mode, and requested mode is sleep mode, then follow these normal mode to sleep mode steps.

Select sleep mode and return	MSR	SLEEP	0x04	0	1b'1
If current mode is sleep mode, and requested mode is normal mode, then follow these sleep mode too normal mode steps.

Select normal mode and return.	MSR	SLEEP \| LBACK \| SNOOP	0x04	2:0	3b'000
If the mode transition is not any of the two cases above, CAN must enter configuration mode before switching into the target operation mode.
Set configuration mode	SRR	CEN \| SRST	0x00	1:0	2b'00
Check the device mode. Refer to the CAN Get Mode. If the device is not entered into configuration mode, return. If entered, then follow these steps to set the requested mode.
To set sleep mode
Select sleep mode.	MSR	SLEEP	0x04	0	1b'1
Enable CAN.	SRR	CEN	0x00	1	1b'1
To set normal mode
Select normal mode.	MSR	SLEEP \| LBACK \| SNOOP	0x04	2:0	3b'000
Enable CAN	SRR	CEN	0x00	1	1b'1
To set loopback mode
Select sleep mode.	MSR	LBACK	0x04	1	1b'1
Enable CAN	SRR	CEN	0x00	1	1b'1
To set snoop mode
Select snoop mode.	MSR	SNOOP	0x04	2	1b'1
Enable CAN	SRR	CEN	0x00	1	1b'1

Table 20-12: Check CAN FIFO is Full
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
Read status register.	SR	TXFLL	0X18	10	READ operation
If TXFLL is set, then the FIFO is full. Else, the FIFO is not full.

Table 20-13: CAN Frame Send
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
Check if the CAN FIFO is full to make sure there is room in the FIFO. Refer to Check CAN FIFO is Full.
Program TXFIFO_ID.	TXFIFO_ID	IDH \| SRRRTR \| IDE \| IDL \| RTR	0x30	31:0	0x20000000 (hex)
Program TXFIFO_DLC.	TXFIFO_DLC	DLC	0x34	31:28	4b'1000
Program TXFIFO_DATA1.	TXFIFO_DATA1	DB0 \| DB1 \| DB2 \| DB3	0x38	31:0	Data
Program TXFIFO_DATA2.	TXFIFO_DATA2	DB4 \| DB5\| DB6 \| DB7	0x3c	31:0	Data

Table 20-14: CAN Check RX Empty
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
Read ISR.	ISR	RXNEMP	0x1C	7	Read operation
If the RXNEMP bit is set, then the RX is not empty. Else, the RX FIFO is empty.

Table 20-15: CAN Receive Frame
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
Check RX empty to make sure data is present (refer CAN Check RX empty)
Read RXFIFO_ID.	RXFIFO_ID	IDH \| SRRRTR \| IDE \| IDL \| RTR	0x50	31:0	Read
Read RXFIFO_DLC.	RXFIFO_DLC	DLC \| RXT	0x54	31:0	Read
Read RXFIFO_DATA1.	RXFIFO_DATA1	DB0 \| DB1 \| DB2 \| DB3	0x58	31:0	Read
Read RXFIFO_DATA2.	RXFIFO_DATA2	DB4 \| DB5\| DB6 \| DB7	0x5C	31:0	Read
Clear RXNEMP bit.	ISR	RXNEMP	0x1C	7	1'b0

Table 20-16: CAN Setup Interrupt System
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
Initialize GIC. Refer to the GIC section.
Register GIC interrupt handler. Refer to the GIC section.
Register CAN interrupt handler with the GIC.
Enable GIC. Refer to the GIC section.
Enable processor interrupts.

Table 20-17: CAN Interrupt Handler
Task	Register	Register Field	Register Offset	Bits	Value (Binary)
Read ISR (status).	ISR	All	0x1C	14:0	Read
Get enabled interrupts list (pendingintr and status).	IER	All	0x20	14:0	Read
Clear all interrupts.	ICR	All	0x24	14:0	pendingintr
If error interrupt is set (bit CERROR), notify application the error interrupt has been set.
Read error status (esr_status).	ESR	0x14	All	4:0	Read
Clear error status.	ESR	0x14	esr_status	4:0	esr_status
If the bus off interrupt is set (BSOFF bit), return from interrupt.
If water mark full OR RXNEMP interrupts set, receive frame. Refer to CAN Receive Frame.
If TXOK interrupt is set notify application that TX is ok.