Miscellaneous Signals and Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID: UG1085
Release Date: 2023-12-21
Revision: 2.4 English

Table: Miscellaneous Signals and Interfaces lists the miscellaneous signals and interfaces. For details, see Table: Transmit FIFO Interface to PL, Table: Transmit FIFO Interface to PL Status, and Table: Receive FIFO Interface to the PL.

Table 2-8: Miscellaneous Signals and Interfaces
Name	Count	Source	Destination	Description
GEM FIFO	87 (x4)	GEM, PL	GEM, PL	Ethernet RX and TX FIFO packet streams.
GEM 1588	136	GEM, PL	GEM, PL	Ethernet 94-bit IEEE 1588 timestamp read by PL interface, PTP event frame interface, and timestamp clock interface.
DDR Refresh Req	2	PL	FPD	DDR memory controller external refresh request signals.
DDR Refresh Clk	1	PL	FPD	DDR memory controller refresh clock.
SEU error alarm	1	PL	CSU	Single event upset error alarm from the PL.
LPD DMA flow control	5	PL	LPD, PL clock, valids, acknowledges	See This Figure.
FPD DMA flow control	5	PL	FPD, PL clock, valids, acknowledges	See This Figure.