The clock control register drives the clocks for all GEM instances including the selection of the TSU interface and source clocks, the FIFO interface clock, SGMII, 1000BASE-SX, 1000BASE-LX, non-SGMII mode, the gem{0:3}_ref_clk (used as the PLL reference clock, the EMIO PLL clock, or the GTX clock), and the gem{0:3}_rx_clock (MIO/EMIO).
Function |
Register Name |
Description |
---|---|---|
Clock control |
iou_slcr.GEM_CLK_CTRL |
GEM clock control. |