Watchdog Timer Programming

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID

UG1085

Release Date

2023-12-21

Revision

2.4 English

The programming steps for the watchdog timer are listed in Table: Watchdog Timer Start through Table: Watchdog Timer Interrupt Handler. Table: Watchdog Timer Interrupt Example lists an example of programming the watchdog timer interrupt.

Table 14-15: Watchdog Timer Start
Task	Register	Register Field	Register Offset	Bits	Value
Enable watchdog timer.	MODE	WDEN	0x00	0	1
Program zero access key.	MODE	ZKEY	0x00	23:12	12'h0ABC

Table 14-16: Watchdog Timer Stop
Task	Register	Register Field	Register Offset	Bits	Value
Disable watchdog timer.	MODE	WDEN	0x00	0	0
Program zero access key.	MODE	ZKEY	0x00	23:12	12'h0ABC

Table 14-17: Watchdog Timer Restart
Task	Register	Register Field	Register Offset	Bits	Value
Restart watchdog timer.	RESTART	RSTKEY	0x08	31:0	1999h

Table 14-18: Check Watchdog Timer Expiry
Task	Register	Register Field	Register Offset	Bits	Value
Read status register.	STATUS	WDZ	0x0C	0	Read operation
Wait until status register WDZ field is set. It is set when the watchdog reaches a zero count.

Table 14-19: Watchdog Timer Enable Signal Output
Task	Register	Register Field	Register Offset	Bits	Value
To enable reset signal.
Enable reset.	MODE	RSTEN	0x00	1	1
To enable IRQ signal.
Enable IRQ.	MODE	IRQEN	0x00	2	1
Program zero access key.	MODE	ZKEY	0x00	23:12	12'h0ABC

Table 14-20: Watchdog Timer Disable Signal Output
Task	Register	Register Field	Register Offset	Bits	Value
If the reset signal to be disabled.
Disable reset.	MODE	RSTEN	0x00	1	0
If IRQ signal to be disabled.
Disable IRQ.	MODE	IRQEN	0x00	2	0
Program access value.	MODE	ZKEY	0x00	23:12	12'h0ABC

Table 14-21: Watchdog Timer Set Control Value
Task	Register	Register Field	Register Offset	Bits	Value
To set clock prescale value.
Read clock prescale value.	CONTROL	CLK_SEL	0x04	1:0	Value to be written
To set counter reset value.
Read counter reset value.	CONTROL	CRV	0x04	13:2	Value to be set
Program new zero access key.	CONTROL	CKEY	0x04	25:14	12'h0248

Table 14-22: Watchdog Timer Get Control Value
Task	Register	Register Field	Register Offset	Bits	Value
To read clock prescale value.
Read clock prescale value.	CONTROL	CLK_SEL	0x04	1:0	Read operation
To read counter reset value.
Read counter reset value.	CONTROL	CRV	0x04	13:2	Read operation

Table 14-23: Watchdog Timer Self Test
Task	Register	Register Field	Register Offset	Bits	Value
Read zero mode register.	MODE	All	0x00	31:0	Read
Select the number of clock cycles that the internal system reset is held active after it is invoked.
Write back reset length.	MODE	All	0x00	31:0	Mode \| RSTLN
Read back zero mode register.	MODE	All	0x00	6:4	Read
Write to the zero mode register is only valid if zero access key (ZKEY) is set to 0xABC.
Write with key value.	MODE	All	0x00	31:0	Mode \| RSTLN\| ZKEY
Read back zero mode register.	MODE	All	0x00	31:0	Read
Read ZKEY and compare with 0xABC. If it is matching, hardware test passed. Otherwise, hardware test failed and hardware locking feature is functional.
Program original register value and return success.	MODE	All	0x00	31:0	Mode \| ZKEY

Table 14-24: Watchdog Timer Setup Interrupts
Task	Register	Register Field	Register Offset	Bits	Value
Initialize generic interrupt controller (GIC) controller.
Set GIC priority trigger type.
Register GIC interrupt handler.
Connect GIC to the snoop control unit (SCU) watchdog timer interrupt handler.
Enable GIC interrupt.

Table 14-25: Watchdog Timer Interrupt Handler
Task	Register	Register Field	Register Offset	Bits	Value
Notify the application by setting a global variable.

Table 14-26: Watchdog Timer Interrupt Example
Task	Register	Register Field	Register Offset	Bits	Value
Perform self test. Refer to Watchdog Timer Self Test.
Set the initial counter restart to the smallest value. Refer to Watchdog Timer Set Control Value.
Set the initial divider ratio at the smallest value. Refer to Watchdog Timer Set Control Value.
Disable the reset output. Refer to Watchdog Timer Disable Signal Output.
Start watchdog timer device. Refer to Watchdog Timer Start.
Restart watchdog timer. Refer to Watchdog Timer Restart.
Check if watchdog timer is expired. Refer to Check Watchdog Timer Expiry.
Stop watchdog timer. Refer to Watchdog Timer Stop.
Set up interrupt system. Refer to Watchdog Timer Setup Interrupts.
Enable IRQ output. Refer to Watchdog Timer Enable Signal Output.
Start watchdog timer device. Refer to Watchdog Timer Start.
Restart watchdog timer. Refer to Watchdog Timer Restart.
Wait till watchdog timer IRQ handler notification. Refer to Watchdog Timer Interrupt Handler.
If no notification is received,
Disable interrupts and return failure.
Else, if test passed,
Restart watchdog timer. Refer to Watchdog Timer Restart.
Verify that the watchdog timer does not time out when restarted all the time.
Restart watchdog timer. Refer to Watchdog Timer Restart.
If more time has passed than it took for it to expire when not restarted in the previous test, then stop the timer.
Check if watchdog timer is expired. Refer to Check Watchdog Timer Expiry.
If no notification from interrupt handler, disable interrupts and return success.