GMII/MII Interface via EMIO

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID

UG1085

Release Date

2023-12-21

Revision

2.4 English

There are options to provide further external interface standard support by linking the GMII signals on the EMIO interface to the PL. Logic can be designed and connected to generate other interface standards on the PL pins. TBI support can be provided by connecting the GMII to a TBI compatible logic core in the PL, which provides the PCS functions required for ten-bit interfacing to an external PHY via the PL pins. SGMII or 1000 Base-X support can be provided by connecting the GMII to an SGMII or 1000 Base-X compatible logic core, which provides the required PCS functions and signal adaptation and drives an MGT for serial interfacing to an external PHY.

An example illustrating the GMII interface connections through the PL to the PL pins is shown in This Figure. Ethernet GMII/MII interface signals routed through the EMIO are identified in Table: Ethernet GMII/MII Interface Signals via EMIO Interface.

Figure 34-11: GMII Interface via EMIO Connections
X-Ref Target - Figure 34-11

Table 34-14: Ethernet GMII/MII Interface Signals via EMIO Interface
Interface Signal	Reference Clock	Default Controller Input Value	EMIO Interface Signals
Interface Signal	Reference Clock	Default Controller Input Value	Name	I/O
Carrier sense	~		emio_enet{0:3}_gmii_crs	I
Collision detect	~		emio_enet{0:3}_gmii_col	I
Controller interrupt wake-up	~		emio_enet{0:3}_ext_int_in	I
Speed mode (2:0)⁽³⁾	~		emio_enet{0:3}_speed_mode	O
Tx Signals
Tx Clock	~		emio_enet{0:3}_gmii_tx_clk	I
Tx Data (7:0)	Tx Clk	~	emio_enet{0:3}_gmii_txd	O
Tx Enable	Tx Clk	~	emio_enet{0:3}_gmii_tx_en	O
Tx Error	Tx Clk	~	emio_enet{0:3}_gmii_tx_er	O
Rx Signals
Rx Clock	~		emio_enet{0:3}_gmii_rx_clk	I
Rx Data (7:0)	Rx Clk		emio_enet{0:3}_gmii_rxd	I
Rx Data valid	Rx Clk		emio_enet{0:3}_gmii_rx_dv	I
Rx Error	Rx Clk		emio_enet{0:3}_gmii_rx_er	I
TSU
TSU increment control(1:0)	TSU Clk		emio_enet{0:3}_tsu_inc_ctrl(1)	I
TSU clock source from PL	~		fmio_gem_tsu_clk_from_pl	I
TSU timer compare value	TSU Clk		emio_enet{0:3}_tsu_timer_cmp_val	O
TSU clock source from IP Block in the PL	~		emio_enet_tsu_clk	I
Notes: 1.The timer sync strobe registers (tsu_strobe_msb_sec, tsu_strobe_sec, and tsu_strobe_nsec) are loaded with the value of the timer when the input signal emio_enet{0:3}_tsu_inc_ctrl[1:0] = 2'b00. However, the timer sync strobe registers are updated only when emio_enet{0:3}_tsu_inc_ctrl signal toggles between 2b'11 and 2'b00. 2.If using MII, connect the RX[7:4] bits to logic zero. 3.See Table: Speed Mode Bits (2:0) for more information.

Table 34-15: Speed Mode Bits (2:0)
Speed Mode Bits (2:0)	Function
11x	1000 Mb/s using TBI Interface
01x	1000 Mb/s using GMII Interface
001	100 Mb/s using MII Interface
000	10 Mb/s using MII Interface
101	100 Mb/s using SGMII Interface