I/O Coherency

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The I/O (one-way) coherent masters can snoop APU caches through the CCI ACE-Lite slave ports, thus avoiding the need for software to providing coherency by flushing APU caches (when APU data is shared with I/O masters).

All of the PS masters, including the RPU but excluding the full-power DMA controller (FPD DMA), DisplayPort, and S_AXI_HP{0:3}_FPD PS masters, can be optionally configured as I/O coherent. For more information on I/O Coherency, see Zynq UltraScale MPSoC Cache Coherency [Ref 58].