AXI read-burst transfers are translated into SPI flash read instructions that are sent to the Quad-SPI controller TXFIFO. The controller transmit logic retrieves the read instructions from the TXFIFO and passes them to the SPI flash memory device according to the SPI protocol.
The SPI read command is used in linear address mode by writing to the qspi.LQSPI_CFG [INST_CODE]. The supported read command codes and the recommended configuration register settings (qspi.LQSPI_CFG) are listed in Table: Quad-SPI Device Configuration Register Values. The optimal register values for Quad-SPI boot performance using a 33 MHz PS_REF_CLK are shown in Table: Quad-SPI Device Configuration Register Values. These Quad-SPI registers can be programmed in non-secure mode using the register initialization feature in the BootROM header which to speeds the loading of the FSBL/user code. A faster PS_REF_CLK requires adjusting the clock dividers.
The choice of operating mode depends on the capabilities of the Quad-SPI device. For the fastest performance, the I/O fast read modes use 4-bit parallel transfers for address and data. The quad output fast read uses 4-bit parallel transfers for data only. These are still faster than a serial-bit mode.