CoreSight Address Map

This section describes the CoreSight register architecture.

•Each component in the RPU is allocated a 4 KB register space; outside the RPU, each component is allocated a 64 KB register space.

•Within each component register space, there are fixed locations for fixed purposes.

•Address 0x0 on the debug APB is a ROM table, pointing to all other components.

•Each component can be accessed at two address locations on the debug APB.

°When accessed from internal using system map, paddr[31] is forced to 0.

°When accessed from external through JTAG, paddr[31] can be 1 or 0.

•paddr[31]=1 and paddr[31]=0 are subject to different authentications. This is useful for preventing rogue software on the RPU or APU MPCore from interfering with CoreSight components.

CoreSight components are allocated 8 MB of address space from FE80_0000 to FEFF_FFFF. This Figure shows the detailed address space assignment for each debug component. References to the detailed address map within each component space are as follows.