CA training is a feature of LPDDR3 memory used for optimizing the setup and hold times of the CA bus relative to the memory clock. CA training is a special mode of operation in the memory enabled through mode register writes. In this mode, the value of the CA bus captured by the memory during assertion of the chip select (cs_n) is reflected back on the DQ bus. The rising edge CA values are returned on even DQ bits and falling edge CA values are returned on odd DQ bits. Since minimum DQ width is 16, only 8 CA bits can be trained in a session. Consequently, two sessions are required for complete CA training. Completion of CA training is signaled by PGSR0.CADONE. High-level error and warning flags are PGSR0.CAERR and PGSR0.CAWRN, respectively.
CA training deskews the CA bits by adjusting bit delay line (BDL) delays on all the CA bits. The results of this deskew are visible in the AC bit delay line registers, as listed in Table: AC Bit Delay Line Registers.
Table 17-13: AC Bit Delay Line Registers
|
Register
|
Bits
|
Name
|
Description
|
Address
|
|
ACBDLR1
|
[5:0]
|
ACTBD
|
Delay select for the BDL on ACTN. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[9].
|
0xFD080544
|
|
ACBDLR2
|
[5:0]
|
BA0BD
|
Delay select for the BDL on BA[0]. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[6].
|
0xFD080548
|
|
ACBDLR2
|
[13:8]
|
BA1BD
|
Delay select for the BDL on BA[1]. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[7].
|
0xFD080548
|
|
ACBDLR2
|
[21:16]
|
BG0BD
|
Delay select for the BDL on BG[0]. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[8]
|
0xFD080548
|
|
ACBDLR6
|
[5:0]
|
A00BD
|
Delay select for the BDL on address A[0].
|
0xFD080558
|
|
ACBDLR6
|
[13:8]
|
A01BD
|
Delay select for the BDL on address A[1].
|
0xFD080558
|
|
ACBDLR6
|
[21:16]
|
A02BD
|
Delay select for the BDL on address A[2].
|
0xFD080558
|
|
ACBDLR6
|
[29:24]
|
A03BD
|
Delay select for the BDL on address A[3].
|
0xFD080558
|
|
ACBDLR7
|
[5:0]
|
A04BD
|
Delay select for the BDL on address A[4].
|
0xFD08055C
|
|
ACBDLR7
|
[13:8]
|
A05BD
|
Delay select for the BDL on address A[5].
|
0xFD08055C
|
|
ACBDLR7
|
[21:16]
|
A06BD
|
Delay select for the BDL on address A[6].
|
0xFD08055C
|
|
ACBDLR7
|
[29:24]
|
A07BD
|
Delay select for the BDL on address A[7].
|
0xFD08055C
|
|
ACBDLR8
|
[5:0]
|
A08BD
|
Delay select for the BDL on address A[8].
|
0xFD080560
|
|
ACBDLR8
|
[13:8]
|
A09BD
|
Delay select for the BDL on address A[9].
|
0xFD080560
|
|
ACBDLR8
|
[21:16]
|
A10BD
|
Delay select for the BDL on address A[10]. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[0].
|
0xFD080560
|
|
ACBDLR8
|
[29:24]
|
A11BD
|
Delay select for the BDL on address A[11]. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[1].
|
0xFD080560
|
|
ACBDLR9
|
[5:0]
|
A12BD
|
Delay select for the BDL on address A[12]. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[2].
|
0xFD080564
|
|
ACBDLR9
|
[13:8]
|
A13BD
|
Delay select for the BDL on address A[13]. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[3].
|
0xFD080564
|
|
ACBDLR9
|
[21:16]
|
A14BD
|
Delay select for the BDL on address A[14]. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[4].
|
0xFD080564
|
|
ACBDLR9
|
[29:24]
|
A15BD
|
Delay select for the BDL on address A[15]. In LPDDR3 mode, with address copy enabled, this is connected to CA_B[5].
|
0xFD080564
|
CA training also adjusts a locally calibrated delay line (LCDL) to center the clock within the CA bits. The results of this training are listed in Table: AC Local Calibrated Delay Line Register (ACLCDLR).
Table 17-14: AC Local Calibrated Delay Line Register (ACLCDLR)
|
Bits
|
Name
|
Description
|
Address
|
|
[8:0]
|
ACD
|
Address/command delay for AC Macro 0: Delay select for the address/command (ACD) LCDL.
|
0xFD080584
|
|
[24:16]
|
ACD1
|
Address/command delay for AC Macro 1: delay select for the address/command (ACD) LCDL.
|
0xFD080584
|