SWDT I/O Control and Configuration Register Sets - UG1085

Clock Input

LPD_SWDT

LPD_LSBUS_CLK

~

Yes

Yes

IOU_SLCR.WDT_CLK_SEL.

FPD_SWDT

TOPSW_LSBUS_CLK

~

Yes

Yes

FPD_SLCR.WDT_CLK_SEL.

CSU_SWDT

PS_REF_CLK

No

No

LPD_SLCR.CSUPMU_WDT_CLK_SEL.

Reset Output

LPD_SWDT

IRQ [84]

~ [1]

Yes

Yes

Always IRQ and EMIO.
IOU_SLCR.MIO_PIN_xx.

FPD_SWDT

IRQ [145]

~ [1]

Yes

Yes

Always IRQ and EMIO.
IOU_SLCR.MIO_PIN_xx.

CSU_SWDT

IRQ [85]

~ [2]

No

No

Always IRQ.

Configuration Register Sets

LPD_SWDT

~

~

~

~

SWDT register set.

FPD_SWDT

~

~

~

~

WDT register set.

CSU_SWDT

~

~

~

~

CSU_WDT register set.

Notes:

1.The LPD and FPD system watchdog timers can cause a system lockdown to affect the PS_ERROR_STATUS signal.